signal type declaration

Author: kavitha-etl

rtl/axis_gmii_rx.v

@@ -81,57 +81,57 @@ module axis_gmii_rx #
     output wire                     error_bad_fcs,
 
     // debug
-    output [2:0] state_reg_out,
-    output [2:0] state_next_out,
-    output reset_crc_out,
-    output update_crc_out,
+    output wire [2:0] state_reg_out,
+    output wire [2:0] state_next_out,
+    output wire reset_crc_out,
+    output wire update_crc_out,
 
-    output mii_odd_out,
-    output in_frame_out,
+    output wire mii_odd_out,
+    output wire in_frame_out,
 
-    output [DATA_WIDTH-1:0] gmii_rxd_d0_out,
-    output [DATA_WIDTH-1:0] gmii_rxd_d1_out,
-    output [DATA_WIDTH-1:0] gmii_rxd_d2_out,
-    output [DATA_WIDTH-1:0] gmii_rxd_d3_out,
-    output [DATA_WIDTH-1:0] gmii_rxd_d4_out,
+    output wire [DATA_WIDTH-1:0] gmii_rxd_d0_out,
+    output wire [DATA_WIDTH-1:0] gmii_rxd_d1_out,
+    output wire [DATA_WIDTH-1:0] gmii_rxd_d2_out,
+    output wire [DATA_WIDTH-1:0] gmii_rxd_d3_out,
+    output wire [DATA_WIDTH-1:0] gmii_rxd_d4_out,
 
-    output gmii_rx_dv_d0_out,
-    output gmii_rx_dv_d1_out,
-    output gmii_rx_dv_d2_out,
-    output gmii_rx_dv_d3_out,
-    output gmii_rx_dv_d4_out,
+    output wire gmii_rx_dv_d0_out,
+    output wire gmii_rx_dv_d1_out,
+    output wire gmii_rx_dv_d2_out,
+    output wire gmii_rx_dv_d3_out,
+    output wire gmii_rx_dv_d4_out,
 
-    output gmii_rx_er_d0_out,
-    output gmii_rx_er_d1_out,
-    output gmii_rx_er_d2_out,
-    output gmii_rx_er_d3_out,
-    output gmii_rx_er_d4_out,
+    output wire gmii_rx_er_d0_out,
+    output wire gmii_rx_er_d1_out,
+    output wire gmii_rx_er_d2_out,
+    output wire gmii_rx_er_d3_out,
+    output wire gmii_rx_er_d4_out,
 
-    output [DATA_WIDTH-1:0] m_axis_tdata_reg_out,
-    output [DATA_WIDTH-1:0] m_axis_tdata_next_out,
-    output m_axis_tvalid_reg_out,
-    output m_axis_tvalid_next_out,
-    output m_axis_tlast_reg_out, 
-    output m_axis_tlast_next_out,
-    output m_axis_tuser_reg_out, 
-    output m_axis_tuser_next_out,
+    output wire [DATA_WIDTH-1:0] m_axis_tdata_reg_out,
+    output wire [DATA_WIDTH-1:0] m_axis_tdata_next_out,
+    output wire m_axis_tvalid_reg_out,
+    output wire m_axis_tvalid_next_out,
+    output wire m_axis_tlast_reg_out, 
+    output wire m_axis_tlast_next_out,
+    output wire m_axis_tuser_reg_out, 
+    output wire m_axis_tuser_next_out,
 
-    output start_packet_int_reg_out,
-    output start_packet_reg_out,
-    output error_bad_frame_reg_out, 
-    output error_bad_frame_next_out,
-    output error_bad_fcs_reg_out,
-    output error_bad_fcs_next_out,
+    output wire start_packet_int_reg_out,
+    output wire start_packet_reg_out,
+    output wire error_bad_frame_reg_out, 
+    output wire error_bad_frame_next_out,
+    output wire error_bad_fcs_reg_out,
+    output wire error_bad_fcs_next_out,
 
-    output [PTP_TS_WIDTH-1:0] ptp_ts_reg_out,
+    output wire [PTP_TS_WIDTH-1:0] ptp_ts_reg_out,
 
-    output [31:0] crc_state_out,
-    output [31:0] crc_next_out,
+    output wire [31:0] crc_state_out,
+    output wire [31:0] crc_next_out,
 
-    output clk_enable_out,
-    output mii_select_out,
-    
-    output cfg_rx_enable_out    
+    output wire clk_enable_out,
+    output wire mii_select_out,
+
+    output wire cfg_rx_enable_out    
 );
 
 // bus width assertions