IDELAYE3 integration #7
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ollie-etl
approved these changes
Jul 15, 2025
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Added IDELAYE3 instantiation in the iddr module (rtl/iddr.v) to manage clock-to-data delay for Ultrascale and Ultrascale+ devices. This enhances compatibility and timing performance on these architectures.
Replaced the legacy IDDR buffer with custom DDR logic, as IDELAYE3 is not supported with IDDR in Ultrascale+ devices.
Set delay mode to "COUNT" and determined an optimal fixed delay value through a sweep of various count values during testing.
Removed redundant parameters for code simplification and maintainability.
This update ensures better synthesis and timing behaviour on Ultrascale and Ultrascale+ FPGAs.