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eusanchez/README.md

πŸ‘‹ Hi there! I'm Ana Sanchez

πŸŽ“ I'm a graduate student in Computer Engineering at Texas A&M University, starting Fall 2025.
πŸ”§ Passionate about machine learning, digital design, hardware verification, and building strong foundations in system-level engineering.


πŸ’Ό Experience Highlights

  • Intel Corporation – IP Logic Design Engineer
  • Siemens Digital Industries Software – Design and Verification Engineer
  • HPE Aruba Networking – Engineering Verification Intern
  • University of Costa Rica – Circuit Design Instructor
    • Taught digital circuits and guided students in hardware design fundamentals.

πŸ” Looking for Opportunities

I'm open to internships and collaborative projects in the areas of:

  • RTL Design & Verification
  • SoC Development
  • Computer Architecture
  • Machine Learning for Hardware
  • EDA Tools and Automation

πŸ› οΈ Skills & Tools

πŸ’» Programming & Scripting

  • Languages: Python, Bash, C, C++, Tcl
  • Hardware Design: Verilog, SystemVerilog, UVM
  • Editors: Vim

πŸ”Ž Verification & Design

  • UVM methodology
  • Digital design and verification workflows
  • RTL to GDS flow (learning in progress)

🧠 Machine Learning

  • Python libraries: scikit-learn, xgboost, numpy
  • Currently expanding my knowledge in ML applications for hardware

🌱 Currently Working On

I'm currently reinforcing my fundamentals in both hardware design and software engineering, while exploring intersections like:

  • ML-enhanced verification
  • Design automation and flow optimization

πŸ“« Connect with me on LinkedIn
Feel free to reach out for opportunities or collaboration!

Pinned Loading

  1. 21_days_RTL 21_days_RTL Public

    https://quicksilicon.in/course/21daysofrtl

    SystemVerilog

  2. csce689_iSogCLR csce689_iSogCLR Public

    Forked from xywei00/csce689_iSogCLR

    Cloning the repo, for final term project to add novelty

    Python 1

  3. LeetCode_answers LeetCode_answers Public

    Leetcode results by me.

    Python

  4. SystemVerilog_Exercises SystemVerilog_Exercises Public

    Ran in EDAPlayground

    SystemVerilog

  5. uvm_study uvm_study Public

    Studying UVM

    SystemVerilog