add riscv ci #4435
Merged
add riscv ci #4435
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
3 participants
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
This PR adds RISCV RVV CI support, including tests for vlen=128, 256, 512, and includes detection of compiler versions for RVV extensions. Some compilation warnings have also been fixed. Additionally, on the Spacemit® X60 @1.6 GHz platform, when the RISC-V Vector (V) extension is enabled along with O3 optimization,unaligned memory access errors may occur if
-DMEM_FORCE_MEMORY_ACCESS=0is not specified. Therefore, this compile-time flag has been added to the CI configuration.This PR is largely identical to a previous one(#4422 ). The reason for closing and resubmitting is that the previous branch was out of sync due to an outdated version. After pulling the latest changes, the PR is re-submitted.