Vivado accelerator axi master interface #683
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…r, and add _LOOP labels
…r, and add _LOOP labels
jmduarte
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…ights, it does not need loading weights in the AXI wrapper
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| newline += indent + '#pragma HLS INTERFACE ap_ctrl_none port=return\n' | ||
| if model.config.get_config_value("IOType") == 'io_stream': | ||
| newline += indent + '#pragma HLS DATAFLOW\n' | ||
| elif '//hls-fpga-machine-learning insert load weights' in line: |
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I would strongly discourage this style of code in the writer. What's the point of templates if they are blank and all the logic is written by the writer? Just clutters the writer. This is much better addressed with a template that contains compile-time constants to select the functionality and just fill out the few lines with specific weights
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Isn't this a copy mainly from vivado_writer.py lines 130-139? Do they both need to change?
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@jmitrevs, yes I moved the code from the vivado_write.py to the vivado_accelerator_write.py.
| newline += indent + '}\n' | ||
| elif io_type == 'io_stream': | ||
| newline = '' | ||
| newline += 'LOAD_INPUT_OUTER_LOOP:\n' |
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Also, can we remove the explicit creation of loops and move that to the template, as suggested above?
| f.close() | ||
| fout.close() | ||
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| def modify_project_cpp(self, model): |
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Lol. Just add a flag to not write the interface in the VivadoWriter instead of this approach.
| if write_txt_file: | ||
| h_file.write("#ifndef __SYNTHESIS__\n") | ||
| h_file.write(var.definition_cpp() + ";\n") | ||
| h_file.write("static " + var.definition_cpp() + ";\n") |
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- Why at all?
- Why like this and not in
definition_cpp()?
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| def predict(self, X, debug=False, profile=False, encode=None, decode=None): | ||
| """ | ||
| Obtain the predictions of the NN implemented in the FPGA. |
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Can we convert this docstring to Google style, like is used elsewhere in the code?
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Description
🐥 👉 Creating a new PR to allow edits from maintainers. Previous PR. 👈 🐥
Extend the VivadoAccelerator backend to support AXI-m data movers for inputs and outputs. An ideal setup is a Xilinx Zynq/ZynqMP board (ARM core + programmable logic).
The backend generates the Python drivers for Pynq-Z2.
Tests
You can test it with this example on Pynq-Z2.