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[RegAllocGreedy] Use MCRegister instead of Register for functions that return a physical register.
The callers of these functions return the value as an MCRegister so this removes some casts from Register to MCRegister.
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‎llvm/lib/CodeGen/RegAllocGreedy.cpp‎

Lines changed: 35 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -1189,9 +1189,9 @@ unsigned RAGreedy::calculateRegionSplitCost(const LiveInterval &VirtReg,
11891189
return BestCand;
11901190
}
11911191

1192-
Register RAGreedy::doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand,
1193-
bool HasCompact,
1194-
SmallVectorImpl<Register> &NewVRegs) {
1192+
MCRegister RAGreedy::doRegionSplit(const LiveInterval &VirtReg,
1193+
unsigned BestCand, bool HasCompact,
1194+
SmallVectorImpl<Register> &NewVRegs) {
11951195
SmallVector<unsigned, 8> UsedCands;
11961196
// Prepare split editor.
11971197
LiveRangeEdit LREdit(&VirtReg, NewVRegs, *MF, *LIS, VRM, this, &DeadRemats);
@@ -1226,7 +1226,7 @@ Register RAGreedy::doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand,
12261226
}
12271227

12281228
splitAroundRegion(LREdit, UsedCands);
1229-
return Register();
1229+
return MCRegister();
12301230
}
12311231

12321232
// VirtReg has a physical Hint, this function tries to split VirtReg around
@@ -1293,9 +1293,9 @@ bool RAGreedy::trySplitAroundHintReg(MCPhysReg Hint,
12931293
/// tryBlockSplit - Split a global live range around every block with uses. This
12941294
/// creates a lot of local live ranges, that will be split by tryLocalSplit if
12951295
/// they don't allocate.
1296-
Register RAGreedy::tryBlockSplit(const LiveInterval &VirtReg,
1297-
AllocationOrder &Order,
1298-
SmallVectorImpl<Register> &NewVRegs) {
1296+
MCRegister RAGreedy::tryBlockSplit(const LiveInterval &VirtReg,
1297+
AllocationOrder &Order,
1298+
SmallVectorImpl<Register> &NewVRegs) {
12991299
assert(&SA->getParent() == &VirtReg && "Live range wasn't analyzed");
13001300
Register Reg = VirtReg.reg();
13011301
bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
@@ -1308,7 +1308,7 @@ Register RAGreedy::tryBlockSplit(const LiveInterval &VirtReg,
13081308
}
13091309
// No blocks were split.
13101310
if (LREdit.empty())
1311-
return Register();
1311+
return MCRegister();
13121312

13131313
// We did split for some blocks.
13141314
SmallVector<unsigned, 8> IntvMap;
@@ -1327,7 +1327,7 @@ Register RAGreedy::tryBlockSplit(const LiveInterval &VirtReg,
13271327

13281328
if (VerifyEnabled)
13291329
MF->verify(this, "After splitting live range around basic blocks", &errs());
1330-
return Register();
1330+
return MCRegister();
13311331
}
13321332

13331333
//===----------------------------------------------------------------------===//
@@ -1414,16 +1414,16 @@ static bool readsLaneSubset(const MachineRegisterInfo &MRI,
14141414
/// be moved to a larger register class.
14151415
///
14161416
/// This is similar to spilling to a larger register class.
1417-
Register RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
1418-
AllocationOrder &Order,
1419-
SmallVectorImpl<Register> &NewVRegs) {
1417+
MCRegister RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
1418+
AllocationOrder &Order,
1419+
SmallVectorImpl<Register> &NewVRegs) {
14201420
const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg());
14211421
// There is no point to this if there are no larger sub-classes.
14221422

14231423
bool SplitSubClass = true;
14241424
if (!RegClassInfo.isProperSubClass(CurRC)) {
14251425
if (!VirtReg.hasSubRanges())
1426-
return Register();
1426+
return MCRegister();
14271427
SplitSubClass = false;
14281428
}
14291429

@@ -1434,7 +1434,7 @@ Register RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
14341434

14351435
ArrayRef<SlotIndex> Uses = SA->getUseSlots();
14361436
if (Uses.size() <= 1)
1437-
return Register();
1437+
return MCRegister();
14381438

14391439
LLVM_DEBUG(dbgs() << "Split around " << Uses.size()
14401440
<< " individual instrs.\n");
@@ -1469,15 +1469,15 @@ Register RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
14691469

14701470
if (LREdit.empty()) {
14711471
LLVM_DEBUG(dbgs() << "All uses were copies.\n");
1472-
return Register();
1472+
return MCRegister();
14731473
}
14741474

14751475
SmallVector<unsigned, 8> IntvMap;
14761476
SE->finish(&IntvMap);
14771477
DebugVars->splitRegister(VirtReg.reg(), LREdit.regs(), *LIS);
14781478
// Assign all new registers to RS_Spill. This was the last chance.
14791479
ExtraInfo->setStage(LREdit.begin(), LREdit.end(), RS_Spill);
1480-
return Register();
1480+
return MCRegister();
14811481
}
14821482

14831483
//===----------------------------------------------------------------------===//
@@ -1567,13 +1567,13 @@ void RAGreedy::calcGapWeights(MCRegister PhysReg,
15671567
/// tryLocalSplit - Try to split VirtReg into smaller intervals inside its only
15681568
/// basic block.
15691569
///
1570-
Register RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
1571-
AllocationOrder &Order,
1572-
SmallVectorImpl<Register> &NewVRegs) {
1570+
MCRegister RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
1571+
AllocationOrder &Order,
1572+
SmallVectorImpl<Register> &NewVRegs) {
15731573
// TODO: the function currently only handles a single UseBlock; it should be
15741574
// possible to generalize.
15751575
if (SA->getUseBlocks().size() != 1)
1576-
return Register();
1576+
return MCRegister();
15771577

15781578
const SplitAnalysis::BlockInfo &BI = SA->getUseBlocks().front();
15791579

@@ -1586,7 +1586,7 @@ Register RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
15861586

15871587
ArrayRef<SlotIndex> Uses = SA->getUseSlots();
15881588
if (Uses.size() <= 2)
1589-
return Register();
1589+
return MCRegister();
15901590
const unsigned NumGaps = Uses.size()-1;
15911591

15921592
LLVM_DEBUG({
@@ -1754,7 +1754,7 @@ Register RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
17541754

17551755
// Didn't find any candidates?
17561756
if (BestBefore == NumGaps)
1757-
return Register();
1757+
return MCRegister();
17581758

17591759
LLVM_DEBUG(dbgs() << "Best local split range: " << Uses[BestBefore] << '-'
17601760
<< Uses[BestAfter] << ", " << BestDiff << ", "
@@ -1788,7 +1788,7 @@ Register RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
17881788
}
17891789
++NumLocalSplits;
17901790

1791-
return Register();
1791+
return MCRegister();
17921792
}
17931793

17941794
//===----------------------------------------------------------------------===//
@@ -1798,19 +1798,20 @@ Register RAGreedy::tryLocalSplit(const LiveInterval &VirtReg,
17981798
/// trySplit - Try to split VirtReg or one of its interferences, making it
17991799
/// assignable.
18001800
/// @return Physreg when VirtReg may be assigned and/or new NewVRegs.
1801-
Register RAGreedy::trySplit(const LiveInterval &VirtReg, AllocationOrder &Order,
1802-
SmallVectorImpl<Register> &NewVRegs,
1803-
const SmallVirtRegSet &FixedRegisters) {
1801+
MCRegister RAGreedy::trySplit(const LiveInterval &VirtReg,
1802+
AllocationOrder &Order,
1803+
SmallVectorImpl<Register> &NewVRegs,
1804+
const SmallVirtRegSet &FixedRegisters) {
18041805
// Ranges must be Split2 or less.
18051806
if (ExtraInfo->getStage(VirtReg) >= RS_Spill)
1806-
return Register();
1807+
return MCRegister();
18071808

18081809
// Local intervals are handled separately.
18091810
if (LIS->intervalIsInOneMBB(VirtReg)) {
18101811
NamedRegionTimer T("local_split", "Local Splitting", TimerGroupName,
18111812
TimerGroupDescription, TimePassesIsEnabled);
18121813
SA->analyze(&VirtReg);
1813-
Register PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
1814+
MCRegister PhysReg = tryLocalSplit(VirtReg, Order, NewVRegs);
18141815
if (PhysReg || !NewVRegs.empty())
18151816
return PhysReg;
18161817
return tryInstructionSplit(VirtReg, Order, NewVRegs);
@@ -1954,12 +1955,10 @@ bool RAGreedy::mayRecolorAllInterferences(
19541955
/// \p Depth gives the current depth of the last chance recoloring.
19551956
/// \return a physical register that can be used for VirtReg or ~0u if none
19561957
/// exists.
1957-
Register RAGreedy::tryLastChanceRecoloring(const LiveInterval &VirtReg,
1958-
AllocationOrder &Order,
1959-
SmallVectorImpl<Register> &NewVRegs,
1960-
SmallVirtRegSet &FixedRegisters,
1961-
RecoloringStack &RecolorStack,
1962-
unsigned Depth) {
1958+
MCRegister RAGreedy::tryLastChanceRecoloring(
1959+
const LiveInterval &VirtReg, AllocationOrder &Order,
1960+
SmallVectorImpl<Register> &NewVRegs, SmallVirtRegSet &FixedRegisters,
1961+
RecoloringStack &RecolorStack, unsigned Depth) {
19631962
if (!TRI->shouldUseLastChanceRecoloringForVirtReg(*MF, VirtReg))
19641963
return ~0u;
19651964

@@ -2058,7 +2057,7 @@ Register RAGreedy::tryLastChanceRecoloring(const LiveInterval &VirtReg,
20582057
LLVM_DEBUG(dbgs() << "tryRecoloringCandidates deleted a fixed register "
20592058
<< printReg(ThisVirtReg) << '\n');
20602059
FixedRegisters.erase(ThisVirtReg);
2061-
return Register();
2060+
return MCRegister();
20622061
}
20632062

20642063
LLVM_DEBUG(dbgs() << "Fail to assign: " << VirtReg << " to "
@@ -2485,7 +2484,7 @@ MCRegister RAGreedy::selectOrSplitImpl(const LiveInterval &VirtReg,
24852484
if (Stage < RS_Spill && !VirtReg.empty()) {
24862485
// Try splitting VirtReg or interferences.
24872486
unsigned NewVRegSizeBefore = NewVRegs.size();
2488-
Register PhysReg = trySplit(VirtReg, Order, NewVRegs, FixedRegisters);
2487+
MCRegister PhysReg = trySplit(VirtReg, Order, NewVRegs, FixedRegisters);
24892488
if (PhysReg || (NewVRegs.size() - NewVRegSizeBefore))
24902489
return PhysReg;
24912490
}

‎llvm/lib/CodeGen/RegAllocGreedy.h‎

Lines changed: 15 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -358,8 +358,9 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public MachineFunctionPass,
358358
BlockFrequency &BestCost,
359359
unsigned &NumCands, bool IgnoreCSR);
360360
/// Perform region splitting.
361-
Register doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand,
362-
bool HasCompact, SmallVectorImpl<Register> &NewVRegs);
361+
MCRegister doRegionSplit(const LiveInterval &VirtReg, unsigned BestCand,
362+
bool HasCompact,
363+
SmallVectorImpl<Register> &NewVRegs);
363364
/// Try to split VirtReg around physical Hint register.
364365
bool trySplitAroundHintReg(MCPhysReg Hint, const LiveInterval &VirtReg,
365366
SmallVectorImpl<Register> &NewVRegs,
@@ -371,18 +372,18 @@ class LLVM_LIBRARY_VISIBILITY RAGreedy : public MachineFunctionPass,
371372
uint8_t &CostPerUseLimit,
372373
SmallVectorImpl<Register> &NewVRegs);
373374
void initializeCSRCost();
374-
Register tryBlockSplit(const LiveInterval &, AllocationOrder &,
375-
SmallVectorImpl<Register> &);
376-
Register tryInstructionSplit(const LiveInterval &, AllocationOrder &,
377-
SmallVectorImpl<Register> &);
378-
Register tryLocalSplit(const LiveInterval &, AllocationOrder &,
379-
SmallVectorImpl<Register> &);
380-
Register trySplit(const LiveInterval &, AllocationOrder &,
381-
SmallVectorImpl<Register> &, const SmallVirtRegSet &);
382-
Register tryLastChanceRecoloring(const LiveInterval &, AllocationOrder &,
383-
SmallVectorImpl<Register> &,
384-
SmallVirtRegSet &, RecoloringStack &,
385-
unsigned);
375+
MCRegister tryBlockSplit(const LiveInterval &, AllocationOrder &,
376+
SmallVectorImpl<Register> &);
377+
MCRegister tryInstructionSplit(const LiveInterval &, AllocationOrder &,
378+
SmallVectorImpl<Register> &);
379+
MCRegister tryLocalSplit(const LiveInterval &, AllocationOrder &,
380+
SmallVectorImpl<Register> &);
381+
MCRegister trySplit(const LiveInterval &, AllocationOrder &,
382+
SmallVectorImpl<Register> &, const SmallVirtRegSet &);
383+
MCRegister tryLastChanceRecoloring(const LiveInterval &, AllocationOrder &,
384+
SmallVectorImpl<Register> &,
385+
SmallVirtRegSet &, RecoloringStack &,
386+
unsigned);
386387
bool tryRecoloringCandidates(PQueue &, SmallVectorImpl<Register> &,
387388
SmallVirtRegSet &, RecoloringStack &, unsigned);
388389
void tryHintRecoloring(const LiveInterval &);

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