chore(test/msr): update Sapphire Rapids baseline with NO_ITS bit

A recent kernel update added this new bit on SPR, so we're updating the
MSR baseline for the cpu template tests.

Signed-off-by: Riccardo Mancini <[email protected]>

Author: Manciukic

tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_5.10guest.csv

@@ -1,7 +1,7 @@
 MSR_ADDR,VALUE
 0x0,0x0
 0x1,0x0
-0x10,0xbae96682
+0x10,0x7c90dcf2
 0x11,0x24a1008
 0x12,0x24a2001
 0x17,0x0
@@ -18,7 +18,7 @@ MSR_ADDR,VALUE
 0xcd,0x3
 0xce,0x80000000
 0xfe,0x508
-0x10a,0xc08e0eb
+0x10a,0x400000000c08e0eb
 0x11e,0xbe702111
 0x122,0x3
 0x140,0x0
@@ -200,7 +200,7 @@ MSR_ADDR,VALUE
 0x619,0x0
 0x639,0x0
 0x641,0x0
-0x6e0,0x18e92c0b0
+0x6e0,0x7d409184
 0x800,0x0
 0x801,0x0
 0x802,0x0
@@ -462,7 +462,7 @@ MSR_ADDR,VALUE
 0xc0000082,0xffffffff81a00080
 0xc0000083,0xffffffff81a015c0
 0xc0000084,0x47700
-0xc0000100,0x7f1687b37740
+0xc0000100,0x3d11f380
 0xc0000101,0xffff88803ec00000
 0xc0000102,0x0
 0xc0000103,0x0

tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_6.1guest.csv

@@ -1,7 +1,7 @@
 MSR_ADDR,VALUE
 0x0,0x0
 0x1,0x0
-0x10,0x7b423550
+0x10,0x6f38b066
 0x11,0x25cb008
 0x12,0x25cc001
 0x17,0x0
@@ -18,7 +18,7 @@ MSR_ADDR,VALUE
 0xcd,0x3
 0xce,0x80000000
 0xfe,0x508
-0x10a,0xc08e0eb
+0x10a,0x400000000c08e0eb
 0x11e,0xbe702111
 0x122,0x3
 0x140,0x0
@@ -200,7 +200,7 @@ MSR_ADDR,VALUE
 0x619,0x0
 0x639,0x0
 0x641,0x0
-0x6e0,0x162fb7dfe
+0x6e0,0x6f8e7c12
 0x800,0x0
 0x801,0x0
 0x802,0x0
@@ -462,7 +462,7 @@ MSR_ADDR,VALUE
 0xc0000082,0xffffffff81a00080
 0xc0000083,0x0
 0xc0000084,0x257fd5
-0xc0000100,0x7fbb7b0e1740
+0xc0000100,0x14cb9380
 0xc0000101,0xffff88803ec00000
 0xc0000102,0x0
 0xc0000103,0x0