Merge branch 'main' into dependabot/cargo/firecracker-b7fbb2bc2f

roypat · web-flow · commit 476f7ea3c15f · 2025-06-04T10:24:40.000Z
diff --git a/tests/conftest.py b/tests/conftest.py
@@ -258,6 +258,17 @@ def waitpkg_bin(test_fc_session_root_path):
     yield waitpkg_bin_path
 
 
+@pytest.fixture(scope="session")
+def msr_reader_bin(test_fc_session_root_path):
+    """Build a binary that reads msrs"""
+    msr_reader_bin_path = os.path.join(test_fc_session_root_path, "msr_reader")
+    build_tools.gcc_compile(
+        "data/msr/msr_reader.c",
+        msr_reader_bin_path,
+    )
+    yield msr_reader_bin_path
+
+
 @pytest.fixture
 def bin_seccomp_paths():
     """Build jailers and jailed binaries to test seccomp.
diff --git a/tests/data/msr/msr_list_SPR_TO_T2_5.10_INTEL_SAPPHIRE_RAPIDS_5.10host_5.10guest.csv b/tests/data/msr/msr_list_SPR_TO_T2_5.10_INTEL_SAPPHIRE_RAPIDS_5.10host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x7e1358a6
 0x11,0x24b8008
diff --git a/tests/data/msr/msr_list_SPR_TO_T2_5.10_INTEL_SAPPHIRE_RAPIDS_5.10host_6.1guest.csv b/tests/data/msr/msr_list_SPR_TO_T2_5.10_INTEL_SAPPHIRE_RAPIDS_5.10host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x6f36e74e
 0x11,0x25cb008
diff --git a/tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_5.10guest.csv b/tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xbae96682
 0x11,0x24a1008
diff --git a/tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_6.1guest.csv b/tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x7b423550
 0x11,0x25cb008
diff --git a/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xfd7a7f6d
 0x11,0x2501008
diff --git a/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xfd7a7f6d
 0x11,0x2501008
diff --git a/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_5.10guest.csv b/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xd2adc3c4
 0x11,0x2a00000
diff --git a/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xd2adc3c4
 0x11,0x2a00000
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xbe7f66e8
 0x11,0x2748008
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xbe7f66e8
 0x11,0x2748008
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_5.10guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xf8c468e6
 0x11,0x2502008
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xf8c468e6
 0x11,0x2502008
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x114970c7a
 0x11,0x2502008
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x114970c7a
 0x11,0x2502008
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_5.10guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x119817846
 0x11,0x2748008
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x119817846
 0x11,0x2748008
diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xc1aa1fac
 0x11,0x2502008
diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xc1aa1fac
 0x11,0x2502008
diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xf68480f8
 0x11,0x2502008
diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xf68480f8
 0x11,0x2502008
diff --git a/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_5.10host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xff34f950
 0x11,0x2748008
diff --git a/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_5.10host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xff34f950
 0x11,0x2748008
diff --git a/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_6.1host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_6.1host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x1000556b4
 0x11,0x2748008
diff --git a/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_6.1host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x1000556b4
 0x11,0x2748008
diff --git a/tests/data/msr/msr_reader.c b/tests/data/msr/msr_reader.c
@@ -0,0 +1,38 @@
+// Copyright 2025 Amazon.com, Inc. or its affiliates. All Rights Reserved.
+// SPDX-License-Identifier: Apache-2.0
+
+// Helper script used to read MSR values from ranges known to contain MSRs.
+
+#include <fcntl.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <unistd.h>
+
+void print_msr(int msr_fd, uint64_t msr) {
+  uint64_t value;
+  if (pread(msr_fd, &value, sizeof(value), msr) == sizeof(value))
+    printf("0x%llx,0x%llx\n", msr, value);
+}
+
+int main() {
+  int msr_fd = open("/dev/cpu/0/msr", O_RDONLY);
+  if (msr_fd < 0)
+    return -1;
+
+  printf("MSR_ADDR,VALUE\n");
+  for (uint64_t msr = 0; msr <= 0xFFF; msr++)
+    print_msr(msr_fd, msr);
+  for (uint64_t msr = 0x10000; msr <= 0x10FFF; msr++)
+    print_msr(msr_fd, msr);
+  for (uint64_t msr = 0xC0000000; msr <= 0xC0011030; msr++)
+    print_msr(msr_fd, msr);
+
+  print_msr(msr_fd, 0x400000000);
+  print_msr(msr_fd, 0x2000000000);
+  print_msr(msr_fd, 0x4000000000);
+  print_msr(msr_fd, 0x8000000000);
+  print_msr(msr_fd, 0x1000000000000);
+  print_msr(msr_fd, 0x3c000000000000);
+  print_msr(msr_fd, 0x80000000000000);
+  print_msr(msr_fd, 0x40000000000000);
+}
diff --git a/tests/data/msr/msr_reader.sh b/tests/data/msr/msr_reader.sh
diff --git a/tests/integration_tests/functional/test_cpu_features_x86_64.py b/tests/integration_tests/functional/test_cpu_features_x86_64.py
@@ -256,7 +256,7 @@ def test_brand_string(uvm_plain_any):
 @pytest.mark.timeout(900)
 @pytest.mark.nonci
 def test_cpu_rdmsr(
-    microvm_factory, cpu_template_any, guest_kernel, rootfs, results_dir
+    msr_reader_bin, microvm_factory, cpu_template_any, guest_kernel, rootfs, results_dir
 ):
     """
     Test MSRs that are available to the guest.
@@ -300,8 +300,8 @@ def test_cpu_rdmsr(
     vm.basic_config(vcpu_count=vcpus, mem_size_mib=guest_mem_mib)
     vm.set_cpu_template(cpu_template_any)
     vm.start()
-    vm.ssh.scp_put(DATA_FILES / "msr_reader.sh", "/tmp/msr_reader.sh")
-    _, stdout, stderr = vm.ssh.run("/tmp/msr_reader.sh", timeout=None)
+    vm.ssh.scp_put(msr_reader_bin, "/tmp/msr_reader")
+    _, stdout, stderr = vm.ssh.run("/tmp/msr_reader")
     assert stderr == ""
 
     # Load results read from the microvm
