pci: add unit tests for MSI-X code

Also, drop some of effectively dead code that Cloud Hypervisor was using
because they were not relying on KVM to handle interrupt controllers.
Finally, fixup some error cases on guest reads which need to return
all-ones when bad accesses happen.

Signed-off-by: Babis Chalios <[email protected]>

Author: bchalios

Cargo.lock

@@ -27,3 +27,4 @@ vm-memory = { version = "0.16.1", features = [
 
 [dev-dependencies]
 serde_test = "1.0.177"
+vmm-sys-util = "0.14.0"

src/pci/Cargo.toml

@@ -843,11 +843,14 @@ impl PciConfiguration {
         if let Some(msix_cap_reg_idx) = self.msix_cap_reg_idx {
             if let Some(msix_config) = &self.msix_config {
                 if msix_cap_reg_idx == reg_idx && offset == 2 && data.len() == 2 {
+                    // 2-bytes write in the Message Control field
                     msix_config
                         .lock()
                         .unwrap()
                         .set_msg_ctl(LittleEndian::read_u16(data));
                 } else if msix_cap_reg_idx == reg_idx && offset == 0 && data.len() == 4 {
+                    // 4 bytes write at the beginning. Ignore the first 2 bytes which are the
+                    // capability id and next capability pointer
                     msix_config
                         .lock()
                         .unwrap()

src/pci/src/configuration.rs

@@ -30,10 +30,7 @@ pub use self::configuration::{
 pub use self::device::{
     BarReprogrammingParams, DeviceRelocation, Error as PciDeviceError, PciDevice,
 };
-pub use self::msix::{
-    Error as MsixError, MsixCap, MsixConfig, MsixConfigState, MsixTableEntry, MSIX_CONFIG_ID,
-    MSIX_TABLE_ENTRY_SIZE,
-};
+pub use self::msix::{Error as MsixError, MsixCap, MsixConfig, MsixConfigState, MsixTableEntry};
 
 /// PCI has four interrupt pins A->D.
 #[derive(Copy, Clone)]