fix: BAR writes through PCI configuration capability #5403
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PCI configuration capability allows a driver to access a BAR without mapping it in virtual address space. The driver issues reads/writes directly within the PCI configuration space (which should always be addressable either via MMIO or Port IO) which the device translates corresponding BAR accesses.
The way this works is that the guests writes the offset and length of a BAR access within the capability structure and then reads/writes data using a 4-bytes dedicated array that also lives in the capability address space.
We had a bug in the logic that handles writes where a guest would program a write of a certain length (L) and then try to perform a write using a buffer where buffer.len() < L. Our logic would then try to perform a write using the slice buffer[..L] which would cause Rust to panic with an out of range exception.
Fix this by taking into account the buffer's length and using a slice with length min(L, buffer.len()).
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