Update fingerprint for AMD #5472
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Codecov Report✅ All modified and coverable lines are covered by tests. Additional details and impacted files@@ Coverage Diff @@
## main #5472 +/- ##
==========================================
- Coverage 82.79% 82.78% -0.01%
==========================================
Files 263 263
Lines 27223 27223
==========================================
- Hits 22538 22537 -1
- Misses 4685 4686 +1
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Manciukic
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The kernel patch [1] passed through CPUID.0x80000021:EAX[5] (VERW_CLEAR) to tell guests that the microcode is applied and the memory form of the VERW instruction can be used to clear the microarchitectural data structures necessary to mitigate TSA-L1 and TSA-SQ. Thanks to it, we can drop the exception for vulnerabilities sysfs check inside guest. In addition to the VERW_CLEAR bit passthrough, the kernel also started always setting CPUID.0x80000021:EAX[9] (NO_SMM_CTL_MSR) since SMM_CTL MSR is not available for KVM guests. [1]: amazonlinux/linux@8d1e0db Signed-off-by: Takahiro Itazuri <[email protected]>
KVM added support for CPUID leaf 0x80000021 [1] and synthesized
TSA_{SQ,L1}_NO bits on ECX [2]. However, the second patch has a bug
where TSA_{SQ,L1}_NO bits are 1st and 2nd bits [3] but exposed as 11th
and 12th bits. This bug happened because it used to be software-defined
word (not hardware-defined). Recently, the kernel added another bit
(X86_FWEATURE_IBPB_EXIT_TO_USER) for VMScape that is not a hardware-
defined bit but a software-defined bit.
We update the fingerprints for now to make the fingerprint test pass,
but will fix the bug. So we'll need to update again once the fix
arrives.
[1]: amazonlinux/linux@6457a8c
[2]: amazonlinux/linux@6fea1a4
[3]: https://www.amd.com/content/dam/amd/en/documents/resources/bulletin/technical-guidance-for-mitigating-transient-scheduler-attacks.pdf
[4]: amazonlinux/linux@ac60717
Signed-off-by: Takahiro Itazuri <[email protected]>
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Manciukic
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JackThomson2
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Oct 8, 2025
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