fix(x86_64): specify IA32_MTRRdefType MSR on boot #5526
Conversation
ShadowCurse
added
Status: Awaiting review
Codecov Report✅ All modified and coverable lines are covered by tests. Please upload reports for the commit dd12568 to get more accurate results. Additional details and impacted files@@ Coverage Diff @@
## main #5526 +/- ##
=======================================
Coverage 82.87% 82.88%
=======================================
Files 270 270
Lines 27780 27784 +4
=======================================
+ Hits 23024 23028 +4
Misses 4756 4756
Flags with carried forward coverage won't be shown. Click here to find out more. ☔ View full report in Codecov by Sentry. 🚀 New features to boost your workflow:
|
The IA32_MTRRdefType MSR describes the default memory type used for physical addresses which are outside of any configured memory ranges, as well as whether MTRRs and fixed ranges are enabled. Without enabling this MSR, guest kernel is not able to change memory types for memory ranges outside main memory. This was causing pmem region to be marked as `uncached-minus` which instructed the cpu to skip all caches (L1, L2, L3) when reading/writing to that memory region. To fix this set IA32_MTRRdefType set to 0x806: - bit 11 enables MTRR - bits 0..7 specify the memory type used by default - value 6 represents `write-back` type Now guest can correctly set pmem memory region to `write-back` memory type. Signed-off-by: Egor Lazarchuk <[email protected]>
Replace hand coded MTRR MSRs with auto generated ones. Signed-off-by: Egor Lazarchuk <[email protected]>
IA32_PAT_MSR can be modified by the guest to change page attributes for memory regions. Signed-off-by: Egor Lazarchuk <[email protected]>
ShadowCurse
requested review from
kalyazin,
pb8o and
xmarcalx
as code owners
|
Added a note to the CHANGELOG. |
Add note about IA32_MTRRdefType MSR to CHANGELOG. Signed-off-by: Egor Lazarchuk <[email protected]>
@ShadowCurse In that case, we should update the doc for boot protocol, I think: https://github.com/firecracker-microvm/firecracker/blob/main/docs/cpu_templates/boot-protocol.md |
Since MTTR-related MSRs are not necessary to boot, having them in the boot protocol doc looks a bit weird. We do it exactly where we apply modification for the boot protocol. It would be better to do it in the CPUID normalization process, but we need to do some refactoring for it and we should rename it since it would modify not only CPUID but also MSRs. But we should have the description somewhere in our doc any way. |
3 participants
Changes
The IA32_MTRRdefType MSR describes the default memory type
used for physical addresses which are outside of any configured
memory ranges, as well as whether MTRRs and fixed ranges
are enabled.
Without enabling this MSR, guest kernel is not able to change
memory types for memory ranges outside main memory. This was
causing pmem region to be marked as
uncached-minuswhichinstructed the cpu to skip all caches (L1, L2, L3) when
reading/writing to that memory region.
To fix this set IA32_MTRRdefType set to 0x806:
write-backtypeNow guest can correctly set pmem memory region to
write-backmemory type.Reason
Fixes incorrect memory type assigment for pmem memory on x86_64.
License Acceptance
By submitting this pull request, I confirm that my contribution is made under
the terms of the Apache 2.0 license. For more information on following Developer
Certificate of Origin and signing off your commits, please check
CONTRIBUTING.md.PR Checklist
tools/devtool checkbuild --allto verify that the PR passesbuild checks on all supported architectures.
tools/devtool checkstyleto verify that the PR passes theautomated style checks.
how they are solving the problem in a clear and encompassing way.
in the PR.
CHANGELOG.md.Runbook for Firecracker API changes.
integration tests.
TODO.rust-vmm.