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L1 arch#1

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fischer-martin wants to merge 55 commits intoarchfrom
L1-arch
Open

L1 arch#1
fischer-martin wants to merge 55 commits intoarchfrom
L1-arch

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fischer-martin and others added 30 commits November 7, 2020 11:24
* cache-entry struct
* default values (cache size, associativity, ...)
information (and some more for better runtime performance)

This is way cleaner than declaring all necessary variables for every
cache and allows us to write more general algorithms.
Also started preparations for LRU replacement strategy
cache misses the number of sets in the cache was reset
instead
This way the function is more general so that it can also be used for
cache writes.
into caches; use paddr instead of vaddr in fill_cache_block()
Since this field was always used indicating the size of a set, the name was adapted accordingly.
    * only flush blocks that were actually valid
    * reset dirty flag after flushing
    * flush to the correct paddr
We do not allocate less memory in the cache block struct, because we forgot to allocate more memory
when we introduced the dirty flag.
Since do_sd() is used to emulate a SD instruction, it should produce only one memory access and thus at most one
cash hit. load_virtual_memory() could result in a hit, or a miss, but store_virtual_memory() would definitely result
in a cache hit. This increases the number of potential cache hits to two, which is not the intended behavior.
fischer-martin and others added 20 commits January 10, 2021 15:00
, since the cache is always in a flushed state during the system calls.
load/store_virtual_memory()
The L1-cache is now only accessed in the emulation of instruction fetches, loads, and stores.
"data-cache" when printing cache statistic
This also fixes the alignment in the output.
the common code into handle_cache_miss()
As a side-effect the function signatures of cache_lookup() and
handle_cache_miss() have been changed by passing the paddr instead of
the tag.
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