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rockchip: rk3576: Properly handle USB controller takeover from BootROM #20

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rockchip: rk3576: Properly handle USB controller takeover from BootROM #20

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17 changes: 15 additions & 2 deletions arch/arm/mach-rockchip/rk3576/rk3576.c
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Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@

#include <dm.h>
#include <misc.h>
#include <linux/delay.h>
#include <asm/armv8/mmu.h>
#include <asm/arch-rockchip/bootrom.h>
#include <asm/arch-rockchip/hardware.h>
Expand Down Expand Up @@ -39,6 +40,10 @@
#define USB_GRF_BASE 0x2601E000
#define USB3OTG0_CON1 0x0030

#define TOP_CRU_BASE 0x27200000
#define TOP_CRU_SOFTRST_CON47 0x0abc


enum {
BROM_BOOTSOURCE_FSPI0 = 3,
BROM_BOOTSOURCE_FSPI1_M1 = 6,
Expand Down Expand Up @@ -190,8 +195,16 @@ int arch_cpu_init(void)
*/
writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);

/* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */
writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
if (read_brom_bootsource_id() == BROM_BOOTSOURCE_USB) {
writel(0x00200020, TOP_CRU_BASE + TOP_CRU_SOFTRST_CON47);
udelay(1000);
writel(0x00200000, TOP_CRU_BASE + TOP_CRU_SOFTRST_CON47);
udelay(1000);
writel(0x000c0008, USB_GRF_BASE + USB3OTG0_CON1);
} else {
/* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */
writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
}

return 0;
}
Expand Down
2 changes: 1 addition & 1 deletion dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -914,7 +914,7 @@
};

&usb_drd0_dwc3 {
dr_mode = "host";
dr_mode = "peripheral";
status = "okay";
};

Expand Down