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@ya-mouse ya-mouse commented Jan 16, 2026

Extend the ARMv8 CPU driver with the following improvements:

  1. Add compatible strings for modern ARM Cortex-A cores:

    • arm,cortex-a53
    • arm,cortex-a55
    • arm,cortex-a72
    • arm,cortex-a73
    • arm,cortex-a75
    • arm,cortex-a76
  2. Implement human-readable CPU name detection by reading the MIDR
    register and mapping known part numbers to descriptive names.

  3. Add clock frequency reporting via the clk framework. The driver
    now probes for an optional clock and reports the CPU frequency
    in cpu_get_info() when available.

  4. Implement get_vendor() callback returning "ARM" as the vendor.

  5. Implement is_current() callback that compares the MPIDR register
    value against the device tree "reg" property to identify if this
    CPU device corresponds to the currently executing CPU.

  6. Add private data structure to track per-CPU state including the
    optional clock reference.

These changes enable proper CPU enumeration and information display
on SoCs using Cortex-A5x and Cortex-A7x cores, which are common in
modern Rockchip, NXP, and other ARM-based platforms.

Change-Id: 6372f41d-a192-4117-9c1a-b5c75db2617a batch-01

@ya-mouse ya-mouse requested a review from alchark January 16, 2026 11:20
@ya-mouse ya-mouse force-pushed the batch-01 branch 7 times, most recently from 0215158 to 323f48d Compare January 17, 2026 17:04
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This change should be a separate patch for upstreaming, and it goes into arch/arm/dts (as an appropriate U-boot specific .dtsi file), not dts/upstream.

Or better yet - make it work in OTG mode, which this particular port really is at the hardware level (and also board markings)

/* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */
writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
if (read_brom_bootsource_id() == BROM_BOOTSOURCE_USB) {
writel(0x00200020, TOP_CRU_BASE + TOP_CRU_SOFTRST_CON47);
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Can we add #define's for the bits here?

udelay(1000);
writel(0x00200000, TOP_CRU_BASE + TOP_CRU_SOFTRST_CON47);
udelay(1000);
writel(0x000c0008, USB_GRF_BASE + USB3OTG0_CON1);
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Ditto. Otherwise it's hard to comprehend why the value here is different from the one under "else"

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Why is it needed now, but hasn't been needed before? Please describe in the commit message what issue this addresses

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Is this purely cosmetic / informational, or do we use this anywhere down the line?

@ya-mouse ya-mouse force-pushed the batch-01 branch 2 times, most recently from 9793cd5 to 4fed021 Compare January 20, 2026 07:58
@ya-mouse ya-mouse changed the title Changes for upstreaming cpu: armv8: Add Cortex-A5x/A7x CPU support and enhance driver functionality Jan 20, 2026
…nality

Extend the ARMv8 CPU driver with the following improvements:

1. Add compatible strings for modern ARM Cortex-A cores:
   - arm,cortex-a53
   - arm,cortex-a55
   - arm,cortex-a72
   - arm,cortex-a73
   - arm,cortex-a75
   - arm,cortex-a76

2. Implement human-readable CPU name detection by reading the MIDR
   register and mapping known part numbers to descriptive names.

3. Add clock frequency reporting via the clk framework. The driver
   now probes for an optional clock and reports the CPU frequency
   in cpu_get_info() when available.

4. Implement get_vendor() callback returning "ARM" as the vendor.

5. Implement is_current() callback that compares the MPIDR register
   value against the device tree "reg" property to identify if this
   CPU device corresponds to the currently executing CPU.

6. Add private data structure to track per-CPU state including the
   optional clock reference.

These changes enable proper CPU enumeration and information display
on SoCs using Cortex-A5x and Cortex-A7x cores, which are common in
modern Rockchip, NXP, and other ARM-based platforms.

Change-Id: 6372f41d-a192-4117-9c1a-b5c75db2617a batch-01
Signed-off-by: Anton Burticica <mouse@ya.ru>
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2 participants