GitHub - florinpavelescu15/RISC-V-Implementation: Implementation of IF, ID, EX, MEM, WB and two stages units used in hazard detection and the forwarding unit, thus realizing a complete RISC-V processor prototype.

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Implementation of IF, ID, EX, MEM, WB and two stages units used in hazard detection and the forwarding unit, thus realizing a complete RISC-V processor prototype.

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Implementation of IF, ID, EX, MEM, WB and two stages units used in hazard detection and the forwarding unit, thus realizing a complete RISC-V processor prototype.

computer-architecture verilog-hdl risc-v hardware-description-language hardware-programming