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simd: riscv: implement RVV intrinsics#9731

Merged

edsiper merged 9 commits intomasterfluent/fluent-bit:masterfrom

cosmo0920-implement-rvv-intrinsicsfluent/fluent-bit:cosmo0920-implement-rvv-intrinsicsCopy head branch name to clipboard

Mar 29, 2025

Conversation Commits9 (9)Checks Files changed

Merged

simd: riscv: implement RVV intrinsics#9731
edsiper merged 9 commits intomasterfrom
cosmo0920-implement-rvv-intrinsics

Commits

Commits on Jan 20, 2025

simd: Implement RVV (RISC-V "Vector") intrinsics
cosmo0920
committed
build: Add C flags for enabling RVV intristics
cosmo0920
committed
utils: Adopt to use RVV extentions for RISC-V
cosmo0920
committed
simd: Add comments for RVV intrinsics
cosmo0920
committed
simd: Specify RVV v0.11 requirement
cosmo0920
committed
simd: Assume VLEN length of RISC-V as 128
cosmo0920
committed
simd: utils: Use macro to avoid magic numbers
cosmo0920
committed
simd: utils: Encapsulate to calculate instruction length for RVV
cosmo0920
committed
simd: Untabify for highbit set instruction
cosmo0920
committed

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