arch/riscv: Fix NMI delivery for SMRNMI hardware

Add SMRNMI extension support and enable NMI delivery on boot.

Changes:
- Add CONFIG_RISCV_ISA_EXT_SMRNMI Kconfig option
- Define SMRNMI CSRs in arch/riscv/include/csr.h
- Set NMIE bit during boot to enable NMI delivery

SMRNMI hardware generates but doesn't deliver NMIs when NMIE=0 (default).
This causes twister test failures and prevents handling of critical
hardware events like watchdog NMIs and ECC errors.

Setting NMIE=1 is mandatory for correct operation on SMRNMI SOCs.

Signed-off-by: Afonso Oliveira <[email protected]>

Author: AFOliveira

arch/riscv/Kconfig.isa

@@ -99,6 +99,17 @@ config RISCV_ISA_EXT_C
 	  which reduces static and dynamic code size by adding short 16-bit
 	  instruction encodings for common operations.
 
+config RISCV_ISA_EXT_SMRNMI
+	bool
+	help
+	  (Smrnmi) - Standard Extension for Resumable Non-Maskable Interrupts
+
+	  The Smrnmi extension adds support for resumable non-maskable
+	  interrupts (RNMIs) to RISC-V. This extension provides architectural
+	  support for hardware error conditions, watchdog timers, and other
+	  critical events that require immediate attention while preserving
+	  the ability to resume execution after handling.
+	  
 config RISCV_ISA_EXT_ZICNTR
 	bool
 	depends on RISCV_ISA_EXT_ZICSR

arch/riscv/core/reset.S

@@ -82,6 +82,10 @@ aa_loop:
 	li t0, __z_interrupt_stack_SIZEOF
 	add sp, sp, t0
 
+#ifdef CONFIG_RISCV_ISA_EXT_SMRNMI
+	csrs CSR_MNSTATUS, MNSTATUS_NMIE
+#endif
+
 #ifdef CONFIG_WDOG_INIT
 	call _WdogInit
 #endif

include/zephyr/arch/riscv/csr.h

@@ -156,6 +156,17 @@
 #define IRQ_COP		12
 #define IRQ_HOST	13
 
+/* SMRNMI CSR addresses */
+#ifdef CONFIG_RISCV_ISA_EXT_SMRNMI
+#define CSR_MNSCRATCH	0x740
+#define CSR_MNEPC	0x741
+#define CSR_MNCAUSE	0x742
+#define CSR_MNSTATUS	0x744
+
+/* MNSTATUS bit fields */
+#define MNSTATUS_NMIE	0x00000008	/* NMI Enable (bit 3) */
+#endif /* CONFIG_RISCV_ISA_EXT_SMRNMI */
+
 #define DEFAULT_RSTVEC	0x00001000
 #define CLINT_BASE	0x02000000
 #define CLINT_SIZE	0x000c0000