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riscv: nsim/rhx: enable F/D, ICCM/DCCM map, XIP; align PMP; update props
- Select RISCV_ISA_EXT_F and D; enable CPU_HAS_FPU(+double) - Default PMP_SLOTS=32 and PMP_GRANULARITY=32 for RHX - Add ICCM/DCCM nodes; mark as zephyr memory regions (FLASH/SRAM) - Point /chosen to ICCM (flash) and DCCM (sram); enable XIP on board - Update CPU riscv,isa to rv32imacfd - Update nsim rhx100.props for ICCM/DCCM, PMP(32/32), F/D and other knobs - Select RISCV_ISA_EXT_SMRNMI in RHX Kconfig - Minor: mark DDR as mmio-sram for completeness Signed-off-by: Afonso Oliveira <[email protected]>
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‎boards/snps/nsim/arc_v/nsim_arc_v_rhx100.dts‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,8 @@
1111
};
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1313
chosen {
14-
zephyr,sram = &ddr0;
14+
zephyr,flash = &iccm0;
15+
zephyr,sram = &dccm0;
1516
zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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};

‎boards/snps/nsim/arc_v/nsim_arc_v_rhx100_defconfig‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
# Copyright (c) 2024 Synopsys, Inc.
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# SPDX-License-Identifier: Apache-2.0
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4-
CONFIG_XIP=n
4+
CONFIG_XIP=y
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CONFIG_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_UART_CONSOLE=y

‎boards/snps/nsim/arc_v/rhx100.dtsi‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,23 @@
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/ {
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ddr0: memory@80000000 {
5+
compatible = "mmio-sram";
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device_type = "memory";
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reg = <0x80000000 0x10000000>; /* 256 MB */
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};
9+
10+
/* Instruction/Data Closely Coupled Memories */
11+
iccm0: iccm@50000000 {
12+
compatible = "zephyr,memory-region", "mmio-sram";
13+
zephyr,memory-region = "FLASH";
14+
zephyr,memory-region-flags = "rx";
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reg = <0x50000000 0x00080000>;
16+
};
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18+
dccm0: dccm@50200000 {
19+
compatible = "zephyr,memory-region", "mmio-sram";
20+
zephyr,memory-region = "SRAM";
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zephyr,memory-region-flags = "rw";
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reg = <0x50200000 0x00080000>;
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};
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};

‎boards/snps/nsim/arc_v/rhx1xx.dtsi‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@
1212
device_type = "cpu";
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reg = <0>;
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clock-frequency = <5000000>;
15-
riscv,isa = "rv32imac_zicsr_zifencei_zba_zbb_zbc_zbs";
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riscv,isa = "rv32imacfd_zicsr_zifencei_zba_zbb_zbc_zbs";
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";

‎boards/snps/nsim/arc_v/support/rhx100.props‎

Lines changed: 43 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,46 @@
11
nsim_isa_family=rv32
2-
nsim_isa_ext=-all.i.m.a.c.s.u.h.zicsr.zifencei.zihintpause.zca.zcb.zcmp.zcmt.zba.zbb.zbc.zbs.zicond.zicbom.zicbop
3-
nsim_isa_big_endian=0
2+
nsim_isa_core=2
3+
nsim_isa_rv_marchid=0x80000402
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nsim_isa_rv_mimpid=0x20100
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nsim_isa_unaligned_option=1
6+
nsim_isa_ext=-all.i.zicsr.zifencei.zihintpause.a.zca.zcf.d.f.h.m.s.u.zcb.zcmp.zcmt.zba.zbb.zbc.zbs.zicond.zfh.zicbom.zicbop
7+
nsim_rv_reset_pc=0x0
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nsim_rv_reset_pc_ext=1
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nsim_isa_dual_issue_option=1
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nsim_isa_fusion_option=1
11+
iccm0_base=0x50000000
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iccm0_size=0x80000
13+
dccm_base=0x50200000
14+
dccm_size=0x80000
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nsim_isa_dccm_mem_cycles=1
16+
icache=0x8000,32,2,a
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nsim_isa_ic_version=1
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nsim_isa_ic_disable_on_reset=1
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dcache=0x4000,32,2,a
20+
nsim_isa_dc_version=1
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nsim_isa_dc_feature_level=2
22+
nsim_has_l0_dcache=1
23+
nsim_isa_dc_mem_cycles=1
24+
nsim_bpu_bc_entries=512
25+
nsim_bpu_pt_entries=8192
26+
nsim_bpu_rs_entries=4
27+
nsim_bpu_tosq_entries=5
28+
nsim_bpu_fb_entries=4
29+
nsim_bpu_debug=1
430
nsim_mmio_base=2560
31+
nsim_mem-interface=ARCV_PMP,num_regions=32,granule=3
32+
nsim_isa_nvm_enabled=1
33+
nsim_isa_nvm_base=0x0
34+
nsim_isa_nvm_size=0x10000000
35+
nsim_rtia_hart_major_prio=1
36+
nsim_rtia_hart_major_prio_width=6
37+
nsim_isa_ext=+xarcvstsp.xarcvsnvi.sstc
38+
nsim_rnmi_vec_ext=0
39+
nsim_rnmi_int_vec=0x800
40+
nsim_isa_has_wb_mem=1
41+
nsim_isa_wb_mem_num_entries=16
42+
nsim_isa_wb_mem_max_outstanding=8
43+
nsim_isa_ext=+smrnmi
44+
45+
# UART must remain consistent with DTS
546
nsim_mem-dev=uart0,kind=16550,base=0x10000000,irq=24
6-
nsim_mem-interface=ARCV_PMP,num_regions=16,granule=1

‎soc/snps/nsim/arc_v/rhx/Kconfig‎

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Original file line numberDiff line numberDiff line change
@@ -15,6 +15,11 @@ config SOC_SERIES_RHX
1515
select RISCV_ISA_EXT_ZBB
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select RISCV_ISA_EXT_ZBC
1717
select RISCV_ISA_EXT_ZBS
18+
select RISCV_ISA_EXT_F
19+
select RISCV_ISA_EXT_D
20+
select RISCV_ISA_EXT_SMRNMI
21+
select CPU_HAS_FPU
22+
select CPU_HAS_FPU_DOUBLE_PRECISION
1823
select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
1924
select INCLUDE_RESET_VECTOR
2025
imply XIP

‎soc/snps/nsim/arc_v/rhx/Kconfig.defconfig‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,17 +3,20 @@
33

44
if SOC_SERIES_RHX
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6+
config XIP
7+
default y
8+
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config SYS_CLOCK_HW_CYCLES_PER_SEC
710
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
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912
config NUM_IRQS
1013
default 32
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1215
config PMP_SLOTS
13-
default 16
16+
default 32
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1518
config PMP_GRANULARITY
16-
default 8
19+
default 32
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1821
config RISCV_PMP
1922
default y

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