More talks, whoohoo

content/downunderflow/2026/talks.csv

@@ -16,3 +16,4 @@ First, we will discuss our 'time protection' project. Contemporary hardware is u
 
 Secondly, we will present our device interface formalism project. Bugs in device drivers cause many vulnerabilities in operating systems, often resulting from violations of the device's protocol or faults in device designs. With a formal model of devices, formal methods can prove the absence of these bugs in drivers, but the accuracy of models derived from datasheets is limited. We solve this by verifying the model against the device's Verilog implementation, simultaneously establishing the absence of device faults.",,
 Sat,16:45,Normal,MockingBoard: A Remote ASIC Prototyping Farm,Daniel Ruelas-Petrisko,"ASIC prototyping flows struggle with complicated toolchain management, ad-hoc debug infrastructure and tight coupling to vendor IP. This talk will describe a flexible approach to engineering emulation clusters, scaling from budget FPGAs to large emulation platforms.",,
+Sat,17:15,Normal,Racquet: A multicore RISC-V using SERV cores,Greg Davill,"Using open source tools, I designed a multicore RISC-V system-on-chip (SoC) in System Verilog, based on the low-area [SERV bit-serial RISC-V CPU](https://github.com/olofk/serv). It was taped out using GF180MCU open source PDK on the first [wafer.space](https://wafer.space) shuttle.",,