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Add OpenPiton power project #283

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Add new project idea in gsoc26-ideas.md
guillemlp Feb 25, 2026
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Clean repeated project
guillemlp Feb 25, 2026
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30 changes: 25 additions & 5 deletions content/gsoc/gsoc26-ideas.md
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Expand Up @@ -135,14 +135,35 @@ This project consists of booting Linux in Qemu, save the memory state, then cont

OpenPiton uses different languages like Verilog, Python, Perl, and C. Verilator C++. Additionally, some background in hardware design is useful.

_Skill Level:_ Medium/Advanced
*Skill Level:* Medium/Advanced

_Duration:_ 350 hours
*Duration:* 350 hours

*Language/Tools:* Verilog, C++, SystemVerilog

*Mentors:* [Guillem López Paradís](mailto:guillem.lopez@bsc.es) and [Jonathan Balkind](mailto:jbalkind@ucsb.edu)

### Enabling OpenROAD-based Power Estimation for OpenPiton Manycore Systems

This project will develop a fully open-source, activity-driven power estimation flow for OpenPiton using OpenROAD and Verilator. The student will port a representative OpenPiton tile (core, cache slice, and NoC router subset) to the OpenROAD-flow-scripts infrastructure to obtain a synthesized and placed-and-routed design targeting an open PDK. Verilator will be used to generate SAIF activity files from representative workloads, which will be annotated in OpenSTA to report switching, internal, and leakage power.

_Language/Tools:_ Verilog, C++, SystemVerilog
The resulting flow will enable reproducible, architecture-level power studies of OpenPiton tiles under realistic physical constraints, supporting the evaluation of cache/NoC parameters and accelerator interfaces within a fully open toolchain.

_Mentors:_ [Guillem López Paradís](mailto:guillem.lopez@bsc.es) and [Jonathan Balkind](mailto:jbalkind@ucsb.edu)
This project can be extended in several directions, for example:
- Automating SAIF generation from simulation workloads (e.g., a Verilator-based regression flow)
- Integrating power reporting into the OpenPiton evaluation framework
- Scaling the flow from a single tile to a small mesh or chiplet quadrant
- Comparing pre- and post-P&R power estimates for architectural design-space exploration

Links: [Openpiton](https://github.com/PrincetonUniversity/openpiton), [SAIF-power-Verilator](https://antmicro.com/blog/2025/07/power-estimation-in-openroad-using-saif-in-verilator)

*Skill Level:* Medium/Advanced

*Duration:* 350 hours

*Language/Tools:* SystemVerilog, TCL, Python, OpenROAD, OpenSTA

*Mentors:* [Guillem López Paradís](mailto:guillem.lopez@bsc.es), [Jonathan Balkind](mailto:jbalkind@ucsb.edu)

### Using AI to Improve Open-Source IP

Expand Down Expand Up @@ -260,7 +281,6 @@ _Language/Tools:_ C++, SystemVerilog

_Mentors:_ [Guillem López Paradís](mailto:guillem.lopez@bsc.es), [Davy Million](mailto:davy.million@cea.fr), [Jonathan Balkind](mailto:jbalkind@ucsb.edu)


### OpenRISC Benchmarking and Performance improvements

The [OpenRISC](https://openrisc.io) CPU architecture has multiple CPU implementations
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