|
247 | 247 | #define ICC_SRE_EL2_SRE (1UL << 0) |
248 | 248 | #define ICC_SRE_EL2_EN (1UL << 3) |
249 | 249 |
|
| 250 | +/* MDCR_EL2 - Hyp Debug Control Register */ |
| 251 | +#define MDCR_EL2_HPMN_MASK 0x1f |
| 252 | +#define MDCR_EL2_HPMN_SHIFT 0 |
| 253 | +#define MDCR_EL2_TPMCR_SHIFT 5 |
| 254 | +#define MDCR_EL2_TPMCR (0x1UL << MDCR_EL2_TPMCR_SHIFT) |
| 255 | +#define MDCR_EL2_TPM_SHIFT 6 |
| 256 | +#define MDCR_EL2_TPM (0x1UL << MDCR_EL2_TPM_SHIFT) |
| 257 | +#define MDCR_EL2_HPME_SHIFT 7 |
| 258 | +#define MDCR_EL2_HPME (0x1UL << MDCR_EL2_HPME_SHIFT) |
| 259 | +#define MDCR_EL2_TDE_SHIFT 8 |
| 260 | +#define MDCR_EL2_TDE (0x1UL << MDCR_EL2_TDE_SHIFT) |
| 261 | +#define MDCR_EL2_TDA_SHIFT 9 |
| 262 | +#define MDCR_EL2_TDA (0x1UL << MDCR_EL2_TDA_SHIFT) |
| 263 | +#define MDCR_EL2_TDOSA_SHIFT 10 |
| 264 | +#define MDCR_EL2_TDOSA (0x1UL << MDCR_EL2_TDOSA_SHIFT) |
| 265 | +#define MDCR_EL2_TDRA_SHIFT 11 |
| 266 | +#define MDCR_EL2_TDRA (0x1UL << MDCR_EL2_TDRA_SHIFT) |
| 267 | +#define MDCR_EL2_E2PB_SHIFT 12 |
| 268 | +#define MDCR_EL2_E2PB_MASK (0x3UL << MDCR_EL2_E2PB_SHIFT) |
| 269 | +#define MDCR_EL2_TPMS_SHIFT 14 |
| 270 | +#define MDCR_EL2_TPMS (0x1UL << MDCR_EL2_TPMS_SHIFT) |
| 271 | +#define MDCR_EL2_EnSPM_SHIFT 15 |
| 272 | +#define MDCR_EL2_EnSPM (0x1UL << MDCR_EL2_EnSPM_SHIFT) |
| 273 | +#define MDCR_EL2_HPMD_SHIFT 17 |
| 274 | +#define MDCR_EL2_HPMD (0x1UL << MDCR_EL2_HPMD_SHIFT) |
| 275 | +#define MDCR_EL2_TTRF_SHIFT 19 |
| 276 | +#define MDCR_EL2_TTRF (0x1UL << MDCR_EL2_TTRF_SHIFT) |
| 277 | +#define MDCR_EL2_HCCD_SHIFT 23 |
| 278 | +#define MDCR_EL2_HCCD (0x1UL << MDCR_EL2_HCCD_SHIFT) |
| 279 | +#define MDCR_EL2_E2TB_SHIFT 24 |
| 280 | +#define MDCR_EL2_E2TB_MASK (0x3UL << MDCR_EL2_E2TB_SHIFT) |
| 281 | +#define MDCR_EL2_HLP_SHIFT 26 |
| 282 | +#define MDCR_EL2_HLP (0x1UL << MDCR_EL2_HLP_SHIFT) |
| 283 | +#define MDCR_EL2_TDCC_SHIFT 27 |
| 284 | +#define MDCR_EL2_TDCC (0x1UL << MDCR_EL2_TDCC_SHIFT) |
| 285 | +#define MDCR_EL2_MTPME_SHIFT 28 |
| 286 | +#define MDCR_EL2_MTPME (0x1UL << MDCR_EL2_MTPME_SHIFT) |
| 287 | +#define MDCR_EL2_HPMFZO_SHIFT 29 |
| 288 | +#define MDCR_EL2_HPMFZO (0x1UL << MDCR_EL2_HPMFZO_SHIFT) |
| 289 | +#define MDCR_EL2_PMSSE_SHIFT 30 |
| 290 | +#define MDCR_EL2_PMSSE_MASK (0x3UL << MDCR_EL2_PMSSE_SHIFT) |
| 291 | +#define MDCR_EL2_HPMFZS_SHIFT 36 |
| 292 | +#define MDCR_EL2_HPMFZS (0x1UL << MDCR_EL2_HPMFZS_SHIFT) |
| 293 | +#define MDCR_EL2_PMEE_SHIFT 40 |
| 294 | +#define MDCR_EL2_PMEE_MASK (0x3UL << MDCR_EL2_PMEE_SHIFT) |
| 295 | +#define MDCR_EL2_EBWE_SHIFT 43 |
| 296 | +#define MDCR_EL2_EBWE (0x1UL << MDCR_EL2_EBWE_SHIFT) |
| 297 | + |
250 | 298 | /* SCTLR_EL2 - System Control Register */ |
251 | 299 | #define SCTLR_EL2_RES1 0x30c50830 |
252 | 300 | #define SCTLR_EL2_M_SHIFT 0 |
|
356 | 404 | /* Assumed to be 0 by locore.S */ |
357 | 405 | #define VTTBR_HOST 0x0000000000000000 |
358 | 406 |
|
359 | | -/* MDCR_EL2 - Hyp Debug Control Register */ |
360 | | -#define MDCR_EL2_HPMN_MASK 0x1f |
361 | | -#define MDCR_EL2_HPMN_SHIFT 0 |
362 | | -#define MDCR_EL2_TPMCR_SHIFT 5 |
363 | | -#define MDCR_EL2_TPMCR (0x1UL << MDCR_EL2_TPMCR_SHIFT) |
364 | | -#define MDCR_EL2_TPM_SHIFT 6 |
365 | | -#define MDCR_EL2_TPM (0x1UL << MDCR_EL2_TPM_SHIFT) |
366 | | -#define MDCR_EL2_HPME_SHIFT 7 |
367 | | -#define MDCR_EL2_HPME (0x1UL << MDCR_EL2_HPME_SHIFT) |
368 | | -#define MDCR_EL2_TDE_SHIFT 8 |
369 | | -#define MDCR_EL2_TDE (0x1UL << MDCR_EL2_TDE_SHIFT) |
370 | | -#define MDCR_EL2_TDA_SHIFT 9 |
371 | | -#define MDCR_EL2_TDA (0x1UL << MDCR_EL2_TDA_SHIFT) |
372 | | -#define MDCR_EL2_TDOSA_SHIFT 10 |
373 | | -#define MDCR_EL2_TDOSA (0x1UL << MDCR_EL2_TDOSA_SHIFT) |
374 | | -#define MDCR_EL2_TDRA_SHIFT 11 |
375 | | -#define MDCR_EL2_TDRA (0x1UL << MDCR_EL2_TDRA_SHIFT) |
376 | | -#define MDCR_EL2_E2PB_SHIFT 12 |
377 | | -#define MDCR_EL2_E2PB_MASK (0x3UL << MDCR_EL2_E2PB_SHIFT) |
378 | | -#define MDCR_EL2_TPMS_SHIFT 14 |
379 | | -#define MDCR_EL2_TPMS (0x1UL << MDCR_EL2_TPMS_SHIFT) |
380 | | -#define MDCR_EL2_EnSPM_SHIFT 15 |
381 | | -#define MDCR_EL2_EnSPM (0x1UL << MDCR_EL2_EnSPM_SHIFT) |
382 | | -#define MDCR_EL2_HPMD_SHIFT 17 |
383 | | -#define MDCR_EL2_HPMD (0x1UL << MDCR_EL2_HPMD_SHIFT) |
384 | | -#define MDCR_EL2_TTRF_SHIFT 19 |
385 | | -#define MDCR_EL2_TTRF (0x1UL << MDCR_EL2_TTRF_SHIFT) |
386 | | -#define MDCR_EL2_HCCD_SHIFT 23 |
387 | | -#define MDCR_EL2_HCCD (0x1UL << MDCR_EL2_HCCD_SHIFT) |
388 | | -#define MDCR_EL2_E2TB_SHIFT 24 |
389 | | -#define MDCR_EL2_E2TB_MASK (0x3UL << MDCR_EL2_E2TB_SHIFT) |
390 | | -#define MDCR_EL2_HLP_SHIFT 26 |
391 | | -#define MDCR_EL2_HLP (0x1UL << MDCR_EL2_HLP_SHIFT) |
392 | | -#define MDCR_EL2_TDCC_SHIFT 27 |
393 | | -#define MDCR_EL2_TDCC (0x1UL << MDCR_EL2_TDCC_SHIFT) |
394 | | -#define MDCR_EL2_MTPME_SHIFT 28 |
395 | | -#define MDCR_EL2_MTPME (0x1UL << MDCR_EL2_MTPME_SHIFT) |
396 | | -#define MDCR_EL2_HPMFZO_SHIFT 29 |
397 | | -#define MDCR_EL2_HPMFZO (0x1UL << MDCR_EL2_HPMFZO_SHIFT) |
398 | | -#define MDCR_EL2_PMSSE_SHIFT 30 |
399 | | -#define MDCR_EL2_PMSSE_MASK (0x3UL << MDCR_EL2_PMSSE_SHIFT) |
400 | | -#define MDCR_EL2_HPMFZS_SHIFT 36 |
401 | | -#define MDCR_EL2_HPMFZS (0x1UL << MDCR_EL2_HPMFZS_SHIFT) |
402 | | -#define MDCR_EL2_PMEE_SHIFT 40 |
403 | | -#define MDCR_EL2_PMEE_MASK (0x3UL << MDCR_EL2_PMEE_SHIFT) |
404 | | -#define MDCR_EL2_EBWE_SHIFT 43 |
405 | | -#define MDCR_EL2_EBWE (0x1UL << MDCR_EL2_EBWE_SHIFT) |
406 | | - |
407 | 407 | #endif /* !_MACHINE_HYPERVISOR_H_ */ |
0 commit comments