RISCV-Reference_SOC_TapeOut_Program_IITGN-VSD

From concepts to Silicon, Shaping INDIA's Semiconductor Program 🤞

📌 Organiser:

It is a program organised by Indian Institute of Technology, Gandhinagar (IITGN) in collaboration with:

• VSD (VLSI System Design)
• SCL
• Synopsys
• Platforms
• RISC-V Core Team
• Efabless

using open-source EDA community tools.

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📌 Program Objectives

The program focuses on hands-on chip design using open-source tools like: Yosys (logic synthesis), OpenROAD/OpenLane (place & route), Magic/KLayout (layout & DRC/LVS checks), with SkyWater 130nm PDK (open-source process design kit) The repository is created as Weekly assignment given under the umberella for RISCV-Reference SOC TapeOut program for 10 weeks.

🧐 Now, let's us see the individual term one by one to 🧠#Ananlyse - 💭 #Think using which the Program is formulated for us.

🖥️⚙️	RISC-V: An open-source Instruction Set Architecture (ISA), widely used in academia and industry for research and processor development.
📦🔗	SoC (System-on-Chip): A complete system (CPU, memory, peripherals, interconnects) integrated onto a single silicon die.
🚀📐	Reference SoC (Caravel): Caravel is a baseline RISC-V SoC design that participants use as a template for customization, learning, and final tapeout. It allows developers to integrate their custom IP (Intellectual Property) into the platform and test its functionality using an open-source toolchain. Caravel is used with Efabless's Open MPW (Multi-Project Wafer) and chipIgnite shuttles, and it's built on the Sky130 technology node from SkyWater Technologies.
🔲🧩	Tapeout: The final step of the IC design flow, where the design is signed off and sent to fabrication.

👉 Essentially, it’s a real-world tapeout training program for students to learn chip design and actually fabricate a working RISC-V chip. VLSI is not just a buzzword but a career that demands patience, depth, and constant learning. With India emerging as a global hub for chip design and the market booming, it’s the right time for aspirants to focus on core skills like RTL, Verification, PD, DFT, AMS, and scripting

📌 📋 Task Progress

📅 Week 0 — Setup & Tools

Task	Description	Status	Help Material	Submission Date
Task0	🛠️ Tools Installation — Installed Iverilog, Yosys, and GTKWave	✅ Done	1. 📄 Week-0 Notes 2. 📄 VSD Installation Guide	20th Sep. 2025
Task1	✍️ will be updated soon	⏳ In Progress	1. 📄 Week-1 Notes (to be added)	TBD

🌟 Key Learnings from Week 0

Here’s what I achieved in the first week of the RISC-V SoC Tapeout Program:

• 🛠️ Tools Installed & Verified: Successfully installed Iverilog, Yosys, and GTKWave, and verified their functionality.
• 💻 Environment Setup: Learned how to set up the basic RTL design and synthesis environment for future experiments.
• 🏗️ System Prepared: Configured the system and prepared it for the upcoming RTL → GDSII flow experiments.

🙏 Acknowledgment

I am thankful to 🤞Kunal Ghosh and Team VLSI System Design (VSD) for the opportunity to participate in the ongoing RISC-V SoC Tapeout Program.

I also acknowledge the support of RISC-V International, India Semiconductor Mission (ISM), VLSI Society of India (VSI), and Efabless for making this initiative possible.

👨‍💻 Participant: Gaurav Purohit