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5 changes: 5 additions & 0 deletions src/cmd/asm/internal/asm/testdata/riscv64.s
Original file line number Diff line number Diff line change
Expand Up @@ -509,6 +509,11 @@ start:
ORCB X5, X6 // 13d37228
REV8 X7, X8 // 13d4836b

// 28.4.3: Carry-less multiplication (Zbc)
CLMUL X5, X6, X7 // b313530a
CLMULH X5, X6, X7 // b333530a
CLMULR X5, X6, X7 // b323530a

// 28.4.4: Single-bit Instructions (Zbs)
BCLR X23, X24, X25 // b31c7c49
BCLR $63, X24 // 131cfc4b
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3 changes: 3 additions & 0 deletions src/cmd/internal/obj/riscv/anames.go

Some generated files are not rendered by default. Learn more about how customized files appear on GitHub.

7 changes: 6 additions & 1 deletion src/cmd/internal/obj/riscv/cpu.go
Original file line number Diff line number Diff line change
Expand Up @@ -669,7 +669,7 @@ const (
ASEXTH
AZEXTH

// 28.4.3: Bitwise Rotation (Zbb)
// 28.4.2: Bitwise Rotation (Zbb)
AROL
AROLW
AROR
Expand All @@ -679,6 +679,11 @@ const (
AORCB
AREV8

// 28.4.3: Carry-less multiplication (Zbc)
ACLMUL
ACLMULH
ACLMULR

// 28.4.4: Single-bit Instructions (Zbs)
ABCLR
ABCLRI
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8 changes: 7 additions & 1 deletion src/cmd/internal/obj/riscv/inst.go

Some generated files are not rendered by default. Learn more about how customized files appear on GitHub.

7 changes: 6 additions & 1 deletion src/cmd/internal/obj/riscv/obj.go
Original file line number Diff line number Diff line change
Expand Up @@ -2621,7 +2621,7 @@ var instructions = [ALAST & obj.AMask]instructionData{
AXNOR & obj.AMask: {enc: rIIIEncoding, ternary: true},
AZEXTH & obj.AMask: {enc: rIIEncoding},

// 28.4.3: Bitwise Rotation (Zbb)
// 28.4.2: Bitwise Rotation (Zbb)
AROL & obj.AMask: {enc: rIIIEncoding, ternary: true},
AROLW & obj.AMask: {enc: rIIIEncoding, ternary: true},
AROR & obj.AMask: {enc: rIIIEncoding, immForm: ARORI, ternary: true},
Expand All @@ -2631,6 +2631,11 @@ var instructions = [ALAST & obj.AMask]instructionData{
AORCB & obj.AMask: {enc: rIIEncoding},
AREV8 & obj.AMask: {enc: rIIEncoding},

// 28.4.3: Carry-less Multiplication (Zbc)
ACLMUL & obj.AMask: {enc: rIIIEncoding, ternary: true},
ACLMULH & obj.AMask: {enc: rIIIEncoding, ternary: true},
ACLMULR & obj.AMask: {enc: rIIIEncoding, ternary: true},

// 28.4.4: Single-bit Instructions (Zbs)
ABCLR & obj.AMask: {enc: rIIIEncoding, immForm: ABCLRI, ternary: true},
ABCLRI & obj.AMask: {enc: iIIEncoding, ternary: true},
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