Fix TCR default value for different exception levels

CHANGELOG.md

@@ -2,12 +2,19 @@
 
 ## Unreleased
 
+### Breaking changes
+
+- Changed order of parameters to `initial-pagetable` macro, to make `TCR` last.
+
 ### Improvements
 
 - If the `initial-pagetable` or `exceptions` features are specified without any of the `elX`
   features, then the exception level will be checked at runtime and the appropriate registers for
   the current EL will be used. The `el1` feature is no longer enabled by default, as this runtime
-  detection should work instead.
+  detection should work instead. Note that different ELs have different TCR registers which aren't
+  laid out entirely the same, so different values must be specified for TCR for each EL.
+- Exposed `enable_mmu!` macro to allow the MMU and caches to be enbled with an arbitrary initial
+  pagetable, rather than using `initial_pagetable!` to declare the static.
 
 ### Bugfixes
 

src/lib.rs

@@ -32,8 +32,17 @@ use core::arch::global_asm;
 #[cfg(not(feature = "initial-pagetable"))]
 use core::arch::naked_asm;
 pub use entry::secondary_entry;
+#[cfg(all(feature = "initial-pagetable", feature = "el1"))]
+pub use pagetable::DEFAULT_TCR_EL1 as DEFAULT_TCR;
+#[cfg(all(feature = "initial-pagetable", feature = "el2"))]
+pub use pagetable::DEFAULT_TCR_EL2 as DEFAULT_TCR;
+#[cfg(all(feature = "initial-pagetable", feature = "el3"))]
+pub use pagetable::DEFAULT_TCR_EL3 as DEFAULT_TCR;
 #[cfg(feature = "initial-pagetable")]
-pub use pagetable::{DEFAULT_MAIR, DEFAULT_SCTLR, DEFAULT_TCR, InitialPagetable};
+pub use pagetable::{
+    DEFAULT_MAIR, DEFAULT_SCTLR, DEFAULT_TCR_EL1, DEFAULT_TCR_EL2, DEFAULT_TCR_EL3,
+    InitialPagetable,
+};
 
 #[cfg(not(feature = "initial-pagetable"))]
 #[unsafe(naked)]