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  1. PCIe-Gen3-Endpoint-Subsystem-Verification PCIe-Gen3-Endpoint-Subsystem-Verification Public

    UVM + DPI-C reference model for PCIe Gen3 endpoint (transaction layer)

    SystemVerilog 1

  2. RISC-V-CPU-Core-UVM-Based-ISA-Compliance-Verification RISC-V-CPU-Core-UVM-Based-ISA-Compliance-Verification Public

    RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.

    SystemVerilog

  3. AXI4-Interconnect-Fabric-Verification-with-UVM AXI4-Interconnect-Fabric-Verification-with-UVM Public

    Synthesizable AXI4 crossbar with a full UVM verification environment — RTL, SVA, coverage, stress, and CI.

    SystemVerilog 1

  4. Async-Fifo-Cdc-Uvm-Verification Async-Fifo-Cdc-Uvm-Verification Public

    UVM-based SystemVerilog testbench for CDC & Async FIFO: SVA assertions, functional coverage, agents/sequences/scoreboard, and VCS/Questa run scripts.

    SystemVerilog

  5. SoC-Flow-Orchestrator-Floorplanning-PDN-CTS-Automation SoC-Flow-Orchestrator-Floorplanning-PDN-CTS-Automation Public

    Python