drivers: ethernet: xlnx_gem: obtain AMBA AHB bus width from config register

Obtain the value for the AMBA AHB bus width (32 bit/64 bit/128 bit) from
the design_cfg5 register at init-time rather than specifying it in the
respective SoC's DT.

Signed-off-by: Immo Birnbaum <[email protected]>

Author: ibirnbaum

drivers/ethernet/eth_xlnx_gem.c

@@ -142,11 +142,6 @@ static int eth_xlnx_gem_dev_init(const struct device *dev)
 #endif
 
 	/* AMBA AHB configuration options */
-	__ASSERT((dev_conf->amba_dbus_width == AMBA_AHB_DBUS_WIDTH_32BIT ||
-		 dev_conf->amba_dbus_width == AMBA_AHB_DBUS_WIDTH_64BIT ||
-		 dev_conf->amba_dbus_width == AMBA_AHB_DBUS_WIDTH_128BIT),
-		 "%s AMBA AHB bus width configuration is invalid",
-		 dev->name);
 	__ASSERT((dev_conf->ahb_burst_length == AHB_BURST_SINGLE ||
 		 dev_conf->ahb_burst_length == AHB_BURST_INCR4 ||
 		 dev_conf->ahb_burst_length == AHB_BURST_INCR8 ||
@@ -946,6 +941,7 @@ static void eth_xlnx_gem_set_initial_nwcfg(const struct device *dev)
 {
 	const struct eth_xlnx_gem_dev_cfg *dev_conf = dev->config;
 	uint32_t reg_val = 0;
+	uint32_t design_cfg5_reg_val;
 
 	if (dev_conf->ignore_ipg_rxer) {
 		/* [30]     ignore IPG rx_er */
@@ -979,10 +975,11 @@ static void eth_xlnx_gem_set_initial_nwcfg(const struct device *dev)
 		/* [23]     Do not copy pause Frames to memory */
 		reg_val |= ETH_XLNX_GEM_NWCFG_PAUSECOPYDI_BIT;
 	}
-	/* [22..21] Data bus width */
-	reg_val |= (((uint32_t)(dev_conf->amba_dbus_width) &
-		   ETH_XLNX_GEM_NWCFG_DBUSW_MASK) <<
-		   ETH_XLNX_GEM_NWCFG_DBUSW_SHIFT);
+	/* [22..21] Data bus width -> obtain from design_cfg5 register */
+	design_cfg5_reg_val = sys_read32(dev_conf->base_addr + ETH_XLNX_GEM_DESIGN_CFG5_OFFSET);
+	design_cfg5_reg_val >>= ETH_XLNX_GEM_DESIGN_CFG5_DBUSW_SHIFT;
+	design_cfg5_reg_val &= ETH_XLNX_GEM_NWCFG_DBUSW_MASK;
+	reg_val |= (design_cfg5_reg_val << ETH_XLNX_GEM_NWCFG_DBUSW_SHIFT);
 	/* [20..18] MDC clock divider */
 	reg_val |= (((uint32_t)dev_conf->mdc_divider &
 		   ETH_XLNX_GEM_NWCFG_MDC_MASK) <<

drivers/ethernet/eth_xlnx_gem_priv.h

@@ -149,27 +149,28 @@
 
 /*
  * Register offsets within the respective GEM's address space:
- * NWCTRL   = gem.net_ctrl       Network Control           register
- * NWCFG    = gem.net_cfg        Network Configuration     register
- * NWSR     = gem.net_status     Network Status            register
- * DMACR    = gem.dma_cfg        DMA Control               register
- * TXSR     = gem.tx_status      TX Status                 register
- * RXQBASE  = gem.rx_qbar        RXQ base address          register
- * TXQBASE  = gem.tx_qbar        TXQ base address          register
- * RXSR     = gem.rx_status      RX Status                 register
- * ISR      = gem.intr_status    Interrupt status          register
- * IER      = gem.intr_en        Interrupt enable          register
- * IDR      = gem.intr_dis       Interrupt disable         register
- * IMR      = gem.intr_mask      Interrupt mask            register
- * PHYMNTNC = gem.phy_maint      PHY maintenance           register
- * LADDR1L  = gem.spec_addr1_bot Specific address 1 bottom register
- * LADDR1H  = gem.spec_addr1_top Specific address 1 top    register
- * LADDR2L  = gem.spec_addr2_bot Specific address 2 bottom register
- * LADDR2H  = gem.spec_addr2_top Specific address 2 top    register
- * LADDR3L  = gem.spec_addr3_bot Specific address 3 bottom register
- * LADDR3H  = gem.spec_addr3_top Specific address 3 top    register
- * LADDR4L  = gem.spec_addr4_bot Specific address 4 bottom register
- * LADDR4H  = gem.spec_addr4_top Specific address 4 top    register
+ * NWCTRL      = gem.net_ctrl       Network Control           register
+ * NWCFG       = gem.net_cfg        Network Configuration     register
+ * NWSR        = gem.net_status     Network Status            register
+ * DMACR       = gem.dma_cfg        DMA Control               register
+ * TXSR        = gem.tx_status      TX Status                 register
+ * RXQBASE     = gem.rx_qbar        RXQ base address          register
+ * TXQBASE     = gem.tx_qbar        TXQ base address          register
+ * RXSR        = gem.rx_status      RX Status                 register
+ * ISR         = gem.intr_status    Interrupt status          register
+ * IER         = gem.intr_en        Interrupt enable          register
+ * IDR         = gem.intr_dis       Interrupt disable         register
+ * IMR         = gem.intr_mask      Interrupt mask            register
+ * PHYMNTNC    = gem.phy_maint      PHY maintenance           register
+ * LADDR1L     = gem.spec_addr1_bot Specific address 1 bottom register
+ * LADDR1H     = gem.spec_addr1_top Specific address 1 top    register
+ * LADDR2L     = gem.spec_addr2_bot Specific address 2 bottom register
+ * LADDR2H     = gem.spec_addr2_top Specific address 2 top    register
+ * LADDR3L     = gem.spec_addr3_bot Specific address 3 bottom register
+ * LADDR3H     = gem.spec_addr3_top Specific address 3 top    register
+ * LADDR4L     = gem.spec_addr4_bot Specific address 4 bottom register
+ * LADDR4H     = gem.spec_addr4_top Specific address 4 top    register
+ * DESIGN_CFG5 = gem.design_cfg5    Design Configuration 5    register
  */
 #define ETH_XLNX_GEM_NWCTRL_OFFSET			0x00000000
 #define ETH_XLNX_GEM_NWCFG_OFFSET			0x00000004
@@ -192,6 +193,7 @@
 #define ETH_XLNX_GEM_LADDR3H_OFFSET			0x0000009C
 #define ETH_XLNX_GEM_LADDR4L_OFFSET			0x000000A0
 #define ETH_XLNX_GEM_LADDR4H_OFFSET			0x000000A4
+#define ETH_XLNX_GEM_DESIGN_CFG5_OFFSET			0x00000290
 
 /*
  * Masks for clearing registers during initialization:
@@ -403,6 +405,13 @@
 #define ETH_XLNX_GEM_PHY_MAINT_REGISTER_ID_SHIFT	18
 #define ETH_XLNX_GEM_PHY_MAINT_DATA_MASK		0x0000FFFF
 
+/*
+ * gem.design_cfg5:
+ * [11 .. 10] Data bus width of the current target SoC
+ *            (mask identical with ETH_XLNX_GEM_NWCFG_DBUSW_MASK)
+ */
+#define ETH_XLNX_GEM_DESIGN_CFG5_DBUSW_SHIFT		10
+
 /* Device initialization macro */
 #define ETH_XLNX_GEM_NET_DEV_INIT(port) \
 ETH_NET_DEVICE_DT_INST_DEFINE(port,\
@@ -431,8 +440,6 @@ static const struct eth_xlnx_gem_dev_cfg eth_xlnx_gem##port##_dev_cfg = {\
 	.phy_poll_interval		= DT_INST_PROP(port, phy_poll_interval),\
 	.defer_rxp_to_queue		= !DT_INST_PROP(port, handle_rx_in_isr),\
 	.defer_txd_to_queue		= DT_INST_PROP(port, handle_tx_in_workq),\
-	.amba_dbus_width		= (enum eth_xlnx_amba_dbus_width)\
-		(DT_INST_PROP(port, amba_ahb_dbus_width)),\
 	.ahb_burst_length		= (enum eth_xlnx_ahb_burst_length)\
 		(DT_INST_PROP(port, amba_ahb_burst_length)),\
 	.hw_rx_buffer_size		= (enum eth_xlnx_hwrx_buffer_size)\
@@ -557,20 +564,6 @@ enum eth_xlnx_link_speed {
 	LINK_1GBIT
 };
 
-/**
- * @brief AMBA AHB data bus width configuration enumeration type.
- *
- * Enumeration type containing the supported width options for the
- * AMBA AHB data bus. This is a configuration item in the controller's
- * net_cfg register.
- */
-enum eth_xlnx_amba_dbus_width {
-	/* The values of this enum are consecutively numbered */
-	AMBA_AHB_DBUS_WIDTH_32BIT = 0,
-	AMBA_AHB_DBUS_WIDTH_64BIT,
-	AMBA_AHB_DBUS_WIDTH_128BIT
-};
-
 /**
  * @brief MDC clock divider configuration enumeration type.
  *
@@ -696,7 +689,6 @@ struct eth_xlnx_gem_dev_cfg {
 	uint8_t				defer_rxp_to_queue;
 	uint8_t				defer_txd_to_queue;
 
-	enum eth_xlnx_amba_dbus_width	amba_dbus_width;
 	enum eth_xlnx_ahb_burst_length	ahb_burst_length;
 	enum eth_xlnx_hwrx_buffer_size	hw_rx_buffer_size;
 	uint8_t				hw_rx_buffer_offset;