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Merge pull request #2373 from Lurcy38/master
Add Support stm32h5 for stm32h573i based on stm32_fsdev G0 implementa…
2 parents 9474db8 + c9c00eb commit 7c181c4

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23 files changed

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-17
lines changed

‎.github/workflows/cmake_arm.yml‎

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@@ -49,6 +49,7 @@ jobs:
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- 'stm32f7'
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- 'stm32g0'
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- 'stm32g4'
52+
- 'stm32h5'
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- 'stm32h7'
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- 'stm32l4'
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- 'stm32u5'

‎.idea/cmake.xml‎

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‎.idea/runConfigurations/stlink.xml‎

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‎hw/bsp/board_mcu.h‎

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@@ -40,8 +40,8 @@
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// Include order follows OPT_MCU_ number
4242
#if TU_CHECK_MCU(OPT_MCU_LPC11UXX, OPT_MCU_LPC13XX, OPT_MCU_LPC15XX) || \
43-
TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC18XX) || \
44-
TU_CHECK_MCU(OPT_MCU_LPC40XX, OPT_MCU_LPC43XX)
43+
TU_CHECK_MCU(OPT_MCU_LPC175X_6X, OPT_MCU_LPC177X_8X, OPT_MCU_LPC18XX) || \
44+
TU_CHECK_MCU(OPT_MCU_LPC40XX, OPT_MCU_LPC43XX)
4545
#include "chip.h"
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4747
#elif TU_CHECK_MCU(OPT_MCU_LPC51UXX, OPT_MCU_LPC54XXX, OPT_MCU_LPC55XX, OPT_MCU_MCXN9)
@@ -54,8 +54,8 @@
5454
#include "nrf.h"
5555

5656
#elif CFG_TUSB_MCU == OPT_MCU_SAMD11 || CFG_TUSB_MCU == OPT_MCU_SAMD21 || \
57-
CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \
58-
CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21
57+
CFG_TUSB_MCU == OPT_MCU_SAMD51 || CFG_TUSB_MCU == OPT_MCU_SAME5X || \
58+
CFG_TUSB_MCU == OPT_MCU_SAML22 || CFG_TUSB_MCU == OPT_MCU_SAML21
5959
#include "sam.h"
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#elif CFG_TUSB_MCU == OPT_MCU_SAMG
@@ -83,6 +83,9 @@
8383
#elif CFG_TUSB_MCU == OPT_MCU_STM32G4
8484
#include "stm32g4xx.h"
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86+
#elif CFG_TUSB_MCU == OPT_MCU_STM32H5
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#include "stm32h5xx.h"
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8689
#elif CFG_TUSB_MCU == OPT_MCU_STM32H7
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#include "stm32h7xx.h"
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‎hw/bsp/stm32g0/boards/stm32g0b1nucleo/board.h‎

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@@ -2,7 +2,7 @@
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* The MIT License (MIT)
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*
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* Copyright (c) 2020, Ha Thach (tinyusb.org)
5-
* Copyright (c) 2034, HiFiPhile
5+
* Copyright (c) 2023, HiFiPhile
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal

‎hw/bsp/stm32g4/family.mk‎

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@@ -1,7 +1,5 @@
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UF2_FAMILY_ID = 0x4c71240a
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ST_FAMILY = g4
3-
DEPS_SUBMODULES += lib/CMSIS_5 hw/mcu/st/cmsis_device_$(ST_FAMILY) hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
4-
53
ST_CMSIS = hw/mcu/st/cmsis_device_$(ST_FAMILY)
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ST_HAL_DRIVER = hw/mcu/st/stm32$(ST_FAMILY)xx_hal_driver
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‎hw/bsp/stm32h5/FreeRTOSConfig/FreeRTOSConfig.h‎

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/*
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* FreeRTOS Kernel V10.0.0
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* Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software. If you wish to use our Amazon
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* FreeRTOS name, please do so in a fair use way that does not cause confusion.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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#ifndef FREERTOS_CONFIG_H
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#define FREERTOS_CONFIG_H
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/*-----------------------------------------------------------
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* Application specific definitions.
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*
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* These definitions should be adjusted for your particular hardware and
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* application requirements.
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*
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* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
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* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
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*
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* See http://www.freertos.org/a00110.html.
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*----------------------------------------------------------*/
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// skip if included from IAR assembler
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#ifndef __IASMARM__
47+
#include "stm32h5xx.h"
48+
#endif
49+
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/* Cortex M23/M33 port configuration. */
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#define configENABLE_MPU 0
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#define configENABLE_FPU 1
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#define configENABLE_TRUSTZONE 0
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#define configMINIMAL_SECURE_STACK_SIZE (1024)
55+
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#define configUSE_PREEMPTION 1
57+
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
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#define configCPU_CLOCK_HZ SystemCoreClock
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#define configTICK_RATE_HZ ( 1000 )
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#define configMAX_PRIORITIES ( 5 )
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#define configMINIMAL_STACK_SIZE ( 128 )
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#define configTOTAL_HEAP_SIZE ( configSUPPORT_DYNAMIC_ALLOCATION*4*1024 )
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#define configMAX_TASK_NAME_LEN 16
64+
#define configUSE_16_BIT_TICKS 0
65+
#define configIDLE_SHOULD_YIELD 1
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#define configUSE_MUTEXES 1
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#define configUSE_RECURSIVE_MUTEXES 1
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#define configUSE_COUNTING_SEMAPHORES 1
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#define configQUEUE_REGISTRY_SIZE 4
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#define configUSE_QUEUE_SETS 0
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#define configUSE_TIME_SLICING 0
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#define configUSE_NEWLIB_REENTRANT 0
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#define configENABLE_BACKWARD_COMPATIBILITY 1
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#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
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#define configSUPPORT_STATIC_ALLOCATION 1
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#define configSUPPORT_DYNAMIC_ALLOCATION 0
78+
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/* Hook function related definitions. */
80+
#define configUSE_IDLE_HOOK 0
81+
#define configUSE_TICK_HOOK 0
82+
#define configUSE_MALLOC_FAILED_HOOK 0 // cause nested extern warning
83+
#define configCHECK_FOR_STACK_OVERFLOW 2
84+
85+
/* Run time and task stats gathering related definitions. */
86+
#define configGENERATE_RUN_TIME_STATS 0
87+
#define configRECORD_STACK_HIGH_ADDRESS 1
88+
#define configUSE_TRACE_FACILITY 1 // legacy trace
89+
#define configUSE_STATS_FORMATTING_FUNCTIONS 0
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/* Co-routine definitions. */
92+
#define configUSE_CO_ROUTINES 0
93+
#define configMAX_CO_ROUTINE_PRIORITIES 2
94+
95+
/* Software timer related definitions. */
96+
#define configUSE_TIMERS 1
97+
#define configTIMER_TASK_PRIORITY (configMAX_PRIORITIES-2)
98+
#define configTIMER_QUEUE_LENGTH 32
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#define configTIMER_TASK_STACK_DEPTH configMINIMAL_STACK_SIZE
100+
101+
/* Optional functions - most linkers will remove unused functions anyway. */
102+
#define INCLUDE_vTaskPrioritySet 0
103+
#define INCLUDE_uxTaskPriorityGet 0
104+
#define INCLUDE_vTaskDelete 0
105+
#define INCLUDE_vTaskSuspend 1 // required for queue, semaphore, mutex to be blocked indefinitely with portMAX_DELAY
106+
#define INCLUDE_xResumeFromISR 0
107+
#define INCLUDE_vTaskDelayUntil 1
108+
#define INCLUDE_vTaskDelay 1
109+
#define INCLUDE_xTaskGetSchedulerState 0
110+
#define INCLUDE_xTaskGetCurrentTaskHandle 1
111+
#define INCLUDE_uxTaskGetStackHighWaterMark 0
112+
#define INCLUDE_xTaskGetIdleTaskHandle 0
113+
#define INCLUDE_xTimerGetTimerDaemonTaskHandle 0
114+
#define INCLUDE_pcTaskGetTaskName 0
115+
#define INCLUDE_eTaskGetState 0
116+
#define INCLUDE_xEventGroupSetBitFromISR 0
117+
#define INCLUDE_xTimerPendFunctionCall 0
118+
119+
/* Define to trap errors during development. */
120+
// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
121+
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
122+
#define configASSERT(_exp) \
123+
do {\
124+
if ( !(_exp) ) { \
125+
volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
126+
if ( (*ARM_CM_DHCSR) & 1UL ) { /* Only halt mcu if debugger is attached */ \
127+
taskDISABLE_INTERRUPTS(); \
128+
__asm("BKPT #0\n"); \
129+
}\
130+
}\
131+
} while(0)
132+
#else
133+
#define configASSERT( x )
134+
#endif
135+
136+
/* FreeRTOS hooks to NVIC vectors */
137+
#define xPortPendSVHandler PendSV_Handler
138+
#define xPortSysTickHandler SysTick_Handler
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#define vPortSVCHandler SVC_Handler
140+
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//--------------------------------------------------------------------+
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// Interrupt nesting behavior configuration.
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//--------------------------------------------------------------------+
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// For Cortex-M specific: __NVIC_PRIO_BITS is defined in mcu header
146+
#define configPRIO_BITS 4
147+
148+
/* The lowest interrupt priority that can be used in a call to a "set priority" function. */
149+
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1<<configPRIO_BITS) - 1)
150+
151+
/* The highest interrupt priority that can be used by any interrupt service
152+
routine that makes calls to interrupt safe FreeRTOS API functions. DO NOT CALL
153+
INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
154+
PRIORITY THAN THIS! (higher priorities are lower numeric values. */
155+
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
156+
157+
/* Interrupt priorities used by the kernel port layer itself. These are generic
158+
to all Cortex-M ports, and do not rely on any particular library functions. */
159+
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
160+
161+
/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
162+
See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
163+
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
164+
165+
#endif

‎hw/bsp/stm32h5/boards/stm32h563nucleo/board.cmake‎

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set(MCU_VARIANT stm32h563xx)
2+
set(JLINK_DEVICE stm32h563zi)
3+
4+
function(update_board TARGET)
5+
target_compile_definitions(${TARGET} PUBLIC
6+
STM32H563xx
7+
)
8+
endfunction()

‎hw/bsp/stm32h5/boards/stm32h563nucleo/board.h‎

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/*
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* The MIT License (MIT)
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*
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* Copyright (c) 2020, Ha Thach (tinyusb.org)
5+
* Copyright (c) 2023, HiFiPhile
6+
*
7+
* Permission is hereby granted, free of charge, to any person obtaining a copy
8+
* of this software and associated documentation files (the "Software"), to deal
9+
* in the Software without restriction, including without limitation the rights
10+
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11+
* copies of the Software, and to permit persons to whom the Software is
12+
* furnished to do so, subject to the following conditions:
13+
*
14+
* The above copyright notice and this permission notice shall be included in
15+
* all copies or substantial portions of the Software.
16+
*
17+
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18+
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19+
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
20+
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21+
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22+
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23+
* THE SOFTWARE.
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*
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* This file is part of the TinyUSB stack.
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*/
27+
28+
#ifndef BOARD_H_
29+
#define BOARD_H_
30+
31+
#ifdef __cplusplus
32+
extern "C" {
33+
#endif
34+
35+
// LED
36+
#define LED_PORT GPIOG
37+
#define LED_PIN GPIO_PIN_4
38+
#define LED_STATE_ON 1
39+
40+
// Button
41+
#define BUTTON_PORT GPIOA
42+
#define BUTTON_PIN GPIO_PIN_0
43+
#define BUTTON_STATE_ACTIVE 0
44+
45+
// UART Enable for STLink VCOM
46+
#define UART_DEV USART1
47+
#define UART_CLK_EN __USART1_CLK_ENABLE
48+
#define UART_GPIO_PORT GPIOA
49+
#define UART_GPIO_AF GPIO_AF7_USART1
50+
51+
#define UART_TX_PIN GPIO_PIN_9
52+
#define UART_RX_PIN GPIO_PIN_10
53+
54+
//--------------------------------------------------------------------+
55+
// RCC Clock
56+
//--------------------------------------------------------------------+
57+
static inline void SystemClock_Config(void) {
58+
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
59+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
60+
61+
/** Configure the main internal regulator output voltage
62+
*/
63+
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
64+
65+
while(!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
66+
67+
/** Initializes the RCC Oscillators according to the specified parameters
68+
* in the RCC_OscInitTypeDef structure.
69+
*/
70+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSE;
71+
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS_DIGITAL;
72+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
73+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
74+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE;
75+
RCC_OscInitStruct.PLL.PLLM = 4;
76+
RCC_OscInitStruct.PLL.PLLN = 250;
77+
RCC_OscInitStruct.PLL.PLLP = 2;
78+
RCC_OscInitStruct.PLL.PLLQ = 2;
79+
RCC_OscInitStruct.PLL.PLLR = 2;
80+
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_1;
81+
RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
82+
RCC_OscInitStruct.PLL.PLLFRACN = 0;
83+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
84+
{
85+
Error_Handler();
86+
}
87+
88+
/** Initializes the CPU, AHB and APB buses clocks
89+
*/
90+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
91+
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2
92+
|RCC_CLOCKTYPE_PCLK3;
93+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
94+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
95+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
96+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
97+
RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
98+
99+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK)
100+
{
101+
Error_Handler();
102+
}
103+
104+
// Configure CRS clock source
105+
__HAL_RCC_CRS_CLK_ENABLE();
106+
RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
107+
RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
108+
RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
109+
RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
110+
RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
111+
RCC_CRSInitStruct.ErrorLimitValue = 34;
112+
RCC_CRSInitStruct.HSI48CalibrationValue = 32;
113+
HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
114+
115+
/* Select HSI48 as USB clock source */
116+
RCC_PeriphCLKInitTypeDef usb_clk = {0 };
117+
usb_clk.PeriphClockSelection = RCC_PERIPHCLK_USB;
118+
usb_clk.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
119+
HAL_RCCEx_PeriphCLKConfig(&usb_clk);
120+
121+
/* Peripheral clock enable */
122+
__HAL_RCC_USB_CLK_ENABLE();
123+
}
124+
125+
#ifdef __cplusplus
126+
}
127+
#endif
128+
129+
#endif /* BOARD_H_ */

‎hw/bsp/stm32h5/boards/stm32h563nucleo/board.mk‎

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MCU_VARIANT = stm32h563xx
2+
3+
CFLAGS += \
4+
-DSTM32H563xx
5+
6+
# For flash-jlink target
7+
JLINK_DEVICE = stm32h563zi

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