[AARCH-24234,herd] Changes to the shareability for DMB and DSB#1691
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relokin merged 1 commit intoherd:masterfrom Mar 4, 2026
Merged
[AARCH-24234,herd] Changes to the shareability for DMB and DSB#1691relokin merged 1 commit intoherd:masterfrom
relokin merged 1 commit intoherd:masterfrom
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I would like to merge this soon. Any reviews would be most welcome! Unless I hear any objections, I will merge this by the end of the day on Tuesday next week. |
This change implements AARCH-24234 as published in the Arm Architecture Reference Manual for A-profile architecture: Known issues in Issue M.a. Since Armv8.0, the memory model is other-multi-copy-atomic and the shareability domain argument for DMB and DSB instructions has become irrelevant for Memory Effects. In other words, for the Arm memory model: * All variants of DMB for reads and writes (DMB SY, DMB OSH, DMB ISH and DMB NSH) provide the same ordering guarantees to software. * All variants of DMB for reads (DMB LD, DMB OSHLD, DMB ISHLD and DMB NSHLD) provide the same ordering guarantees to software. * All variants of DMB for writes (DMB ST, DMB OSHST, DMB ISHST and DMB NSHST) provide the same ordering guarantees to software. And: * All variants of DSB for reads and writes (DSB SY, DSB OSH, DSB ISH and DSB NSH) provide the same ordering guarantees for Memory Effects and DC Effects, but different ordering guarantees for TLBI Effects and IC Effects. * All variants of DSB for reads (DSB LD, DSB OSHLD, DSB ISHLD and DSB NSHLD) provide the same ordering guarantees to software. * All variants of DSB for writes (DSB ST, DSB OSHST, DSB ISHST and DSB NSHST) provide the same ordering guarantees to software. As a result, Arm is proposing to: * Redefine the shareability domain argument for DMB instructions to have no functional meaning. * Deprecate the OSH, ISH, and NSH shareability domain options for DMB instructions. * Rename the shareability domain argument for DSB instructions to the maintenance scope argument to make it clear that this argument is concerned with the ordering requirements of the DSB with regards to TLBI Effects and IC Effects. * Deprecate the OSH, ISH, and NSH maintenance scope for DSB instructions where the required access type is reads. * Deprecate the OSH, ISH, and NSH maintenance scope for DSB instructions where the required access type is writes. * Redefine the SY maintenance scope for DSB instructions where the required access type is reads and writes to have the same functional behavior as the OSH maintenance scope. Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
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This change implements AARCH-24234 as published in the Arm Architecture Reference Manual for A-profile architecture: Known issues in Issue M.a.
Since Armv8.0, the memory model is other-multi-copy-atomic and the shareability domain argument for DMB and DSB instructions has become irrelevant for Memory Effects. In other words, for the Arm memory model:
And:
As a result, Arm is proposing to: