write_mlir: emit src attributes from MLIR locations

rtlil-emit/CMakeLists.txt

@@ -43,6 +43,7 @@ set(LIBS
         ${dialect_libs}
         ${conversion_libs}
         CIRCTRTLIL
+        CIRCTExportVerilog
         MLIRAnalysis
         MLIRCallInterfaces
         MLIRCastInterfaces

rtlil-emit/example/not.mlir

@@ -0,0 +1,9 @@
+// yosys -m rtlil-emit/build/librtlil-emit.so -p "read_mlir rtlil-emit/example/not.mlir; dump"
+module {
+  module @"\\not" {
+    %0 = "rtlil.wire"() <{is_signed = false, name = "\\i1", port_id = 1 : i32, port_input = true, port_output = false, start_offset = 0 : i32, upto = false, width = 1 : i32}> : () -> !rtlil<val[1 : i32]>  loc ("foo.bar":1:2)
+    %1 = "rtlil.wire"() <{is_signed = false, name = "\\o1", port_id = 2 : i32, port_input = false, port_output = true, start_offset = 0 : i32, upto = false, width = 1 : i32}> : () -> !rtlil<val[1 : i32]>
+    "rtlil.cell"(%0, %1) <{name = "$2", parameters = [#rtlil<param "\\A_SIGNED" 0 : i32>, #rtlil<param "\\A_WIDTH" 1 : i32>, #rtlil<param "\\Y_WIDTH" 1 : i32>], ports = ["\\A", "\\Y"], type = "$not"}> : (!rtlil<val[1 : i32]>, !rtlil<val[1 : i32]>) -> ()
+  }
+}
+

rtlil-emit/rtlil-emit.cpp

@@ -14,9 +14,11 @@
 #include "mlir/Target/LLVMIR/Export.h"
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/raw_os_ostream.h"
+#include "llvm/Support/raw_ostream.h"
 
 #include "circt/Dialect/RTLIL/RTLIL.h"
 #include "circt/Dialect/RTLIL/RTLILPasses.h"
+#include "circt/Conversion/ExportVerilog.h"
 
 // Malarkey - I think this is just not generally exposed?
 // TODO move elsewhere?
@@ -191,6 +193,14 @@ class RTLILifier {
       log_error("Unhandled RTLIL dialect value producing op\n");
     }
   }
+  void convertLoc(RTLIL::AttrObject* obj, const mlir::Location& loc) {
+    auto emitter = LocationEmitter(LoweringOptions::LocationInfoStyle::Plain, loc);
+    obj->attributes[RTLIL::ID::src] = RTLIL::Const(emitter.strref().data());
+    // std::string s;
+    // llvm::raw_string_ostream os(s);
+    // loc.print(os);
+    // obj->attributes[RTLIL::ID::src] = RTLIL::Const(os.str());
+  }
 
 public:
   RTLILifier(RTLIL::Design *d) : design(d) {}
@@ -207,6 +217,7 @@ class RTLILifier {
   void convert_cell(RTLIL::Module *mod, rtlil::CellOpInterface op) {
     RTLIL::Cell *c =
         mod->addCell(std::string(op.getCellName()), std::string(op.getCellType()));
+    convertLoc(c, op.getLoc());
     std::vector<std::string> signature;
     for (auto port : op.getCellPorts()) {
       std::string portName = llvm::cast<mlir::StringAttr>(port).str();