irq-bench

For irq benchmark in Linux

Prerequisites

sudo apt-get install linux-headers-$(uname -r)
sudo apt-get install linux-source-$(uname -r)

Build & Integration

How to Build & Integration

Native

$ make clean && make modules

$ make clean && make builtin

Cross-compilation

$ make integrate KERNEL=/path/to/source DTS=/path/to/dts

e.g)

$ make integrate KERNEL=/home/linux DTS=arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dts

Hypervisor benchmark

In a virtualized environment,
the VM kernel running on the hypervisor makes use of the virtual timer.

Arch timer patch

Need linux kernel patch

patches/arm_arch_timer.patch

It uses the physical timer instead of the virtual timer.
Without the timer patch,
benchmarking in a VM refers to the virtual timer,
making the results unreliable.

Hypervisor DTS patch

For interrupt benchmarking, the added irq-bench node must also be present in the hypervisor's device tree.
Additionally, the registers referenced by this node must be configured for passthrough access.
If passthrough is not used, a corresponding emulation driver must be implemented and ported to the hypervisor.

Workaround

These are the workarounds identified so far that need to be applied for each hypervisor.

xen

Xen does not allow duplicate register address definitions in the device tree.
Therefore, the logic for modifying GIC priorities must be removed,
and the reg property should either define only the base address of the PIC or be omitted entirely.
Accordingly, the reg index must also be updated (e.g., GIC: 0 → none, PIC: 1 → 0).
Additionally, to prevent irq-bench from being initialized in Dom0,
the xen,passthrough property must be added to the device tree.

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (C) 2023 Steve Jeong <[email protected]>
 */

#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	/*
	 * reg: Maps the gic base address and the pic base address.
	 *      idx 0: pic_base addr (optional)
	 *
	 * interrupts: 700 is an example.
	 *             However, there are some restrictions to consider:
	 *             The SoC must include a hardware component—such as a PIC—that can generate the interrupt.
	 *             The interrupt number must be unused and physically wired on the actual SoC.
	 */
	irq_bench: irq-bench {
		compatible = "generic,irq-bench";
		/* pic_base */
		reg = <0x0 0x90000000 0x0 0x10000>;
		interrupts = <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
		xen,passthrough;
		status = "okay";
	};
};