feat: add float8_e4m3fnuz and float8_e5m2fnuz dtype support for AMD GPUs#711
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nathanrchn wants to merge 1 commit intohuggingface:mainfrom
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feat: add float8_e4m3fnuz and float8_e5m2fnuz dtype support for AMD GPUs#711nathanrchn wants to merge 1 commit intohuggingface:mainfrom
nathanrchn wants to merge 1 commit intohuggingface:mainfrom
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Add support for the FNUZ (finite, no unsigned zero) float8 variants used by PyTorch. These dtypes differ from the existing float8_e4m3fn and float8_e5m2 types by having no negative zero representation. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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Add support for the FNUZ (finite, no unsigned zero) float8 variants used by PyTorch. These dtypes differ from the existing float8_e4m3fn and float8_e5m2 types by having no negative zero representation.
What does this PR do?
Summary
F8_E4M3FNUZandF8_E5M2FNUZvariants to the RustDtypeenumlib.rs,view.rs,torch.py)Motivation
AMD's CDNA3 architecture (MI300 series) natively uses the FNUZ (finite, no unsigned zero) variants of FP8 rather than the standard
e4m3fn/e5m2formats used by NVIDIA H100 GPUs. These dtypes (torch.float8_e4m3fnuzandtorch.float8_e5m2fnuz) differ by having no negative zero — that bit pattern represents NaN instead.Test plan
cargo testinsafetensors/crate passespytest bindings/python/tests/test_pt_comparison.py -k float8passes (torch >= 2.1 with fnuz support)