feat: split RISC-V extensions into standard and thead modules

- Move standard and T-Head extensions into standard/ and thead/ modules
- Update decoder, handler and tests to use the new Extensions API

Signed-off-by: manchangfengxu <manchangfengxu@openatom.club>

Author: manchangfengxu

robustone-core/src/riscv/decoder.rs

@@ -4,6 +4,7 @@
 //! is implemented as a separate module, making the codebase more maintainable
 //! and easier to extend with new instructions.
 
+use super::extensions::standard::StandardExtensions;
 use super::extensions::{Extensions, InstructionExtension, create_extensions};
 use super::types::*;
 use crate::error::DisasmError;
@@ -36,12 +37,12 @@ impl RiscVDecoder {
 
     /// Create a decoder with full RV32GC support.
     pub fn rv32gc() -> Self {
-        Self::new(Xlen::X32, Extensions::G | Extensions::C)
+        Self::new(Xlen::X32, Extensions::rv32gc())
     }
 
     /// Create a decoder with full RV64GC support.
     pub fn rv64gc() -> Self {
-        Self::new(Xlen::X64, Extensions::G | Extensions::C)
+        Self::new(Xlen::X64, Extensions::rv64gc())
     }
 
     /// Decode a single instruction located at `address`.
@@ -115,7 +116,7 @@ impl RiscVDecoder {
 
         // Try each enabled extension in order
         for extension in &self.extension_handlers {
-            if !extension.is_enabled(self.extensions) {
+            if !extension.is_enabled(&self.extensions) {
                 continue;
             }
 
@@ -213,13 +214,13 @@ impl RiscVDecoder {
             | ((instruction >> 6) & 0x1) << 6          // imm[6] from instruction[6]
             | ((instruction >> 9) & 0x3) << 7; // imm[8:7] from instruction[9:8]
 
-        if !self.extensions.contains(Extensions::C) {
+        if !self.extensions.standard.contains(StandardExtensions::C) {
             eprintln!("Warning: Decoding compressed instruction while C extension is disabled");
         }
 
         // Try each enabled extension for compressed instructions
         for extension in &self.extension_handlers {
-            if !extension.is_enabled(self.extensions) {
+            if !extension.is_enabled(&self.extensions) {
                 continue;
             }
 
@@ -318,16 +319,16 @@ mod tests {
     fn test_refactored_decoder_creation() {
         let decoder = RiscVDecoder::rv32gc();
         assert_eq!(decoder.xlen, Xlen::X32);
-        assert!(decoder.extensions.contains(Extensions::I));
+        assert!(decoder.extensions.standard.contains(StandardExtensions::I));
 
         let decoder = RiscVDecoder::rv64gc();
         assert_eq!(decoder.xlen, Xlen::X64);
-        assert!(decoder.extensions.contains(Extensions::I));
+        assert!(decoder.extensions.standard.contains(StandardExtensions::I));
 
         let decoder = RiscVDecoder::rv64gc();
         assert_eq!(decoder.xlen, Xlen::X64);
-        assert!(decoder.extensions.contains(Extensions::G));
-        assert!(decoder.extensions.contains(Extensions::C));
+        assert!(decoder.extensions.standard.contains(StandardExtensions::G));
+        assert!(decoder.extensions.standard.contains(StandardExtensions::C));
     }
 
     #[test]

robustone-core/src/riscv/extensions/mod.rs

@@ -5,20 +5,43 @@
 
 use super::decoder::{RiscVDecodedInstruction, Xlen};
 use crate::error::DisasmError;
-use bitflags::bitflags;
 
-bitflags! {
-    /// Bitflags representing enabled RISC-V extensions.
-    #[derive(Clone, Copy)]
-    pub struct Extensions: u32 {
-        const G             = Self::I.bits() | Self::M.bits() | Self::A.bits() | Self::F.bits() | Self::D.bits();
-        const I             = 1 << 0;
-        const M             = 1 << 1;
-        const A             = 1 << 2;
-        const F             = 1 << 3;
-        const D             = 1 << 4;
-        const C             = 1 << 5;
-        const XTHEADCONDMOV = 1 << 6;
+// Submodules grouping standard and custom-specific extensions.
+pub mod standard;
+pub mod thead;
+
+use standard::StandardExtensions;
+use thead::THeadExtensions;
+
+/// Aggregated extension configuration passed to RISC-V extension handlers.
+pub struct Extensions {
+    pub(crate) standard: StandardExtensions,
+    pub(crate) thead: THeadExtensions,
+}
+
+impl Extensions {
+    /// Convenience configuration for RV32GC profile with all standard and
+    /// no T-Head custom extensions enabled.
+    pub fn rv32gc() -> Self {
+        Self {
+            standard: StandardExtensions::G | StandardExtensions::C,
+            thead: THeadExtensions::empty(),
+        }
+    }
+
+    /// Convenience configuration for RV64GC profile with all standard and
+    /// no T-Head custom extensions enabled.
+    pub fn rv64gc() -> Self {
+        Self {
+            standard: StandardExtensions::G | StandardExtensions::C,
+            thead: THeadExtensions::empty(),
+        }
+    }
+
+    /// Enables all available T-Head custom extensions on this configuration.
+    pub fn set_thead(mut self) -> Self {
+        self.thead |= THeadExtensions::all();
+        self
     }
 }
 
@@ -81,27 +104,24 @@ pub trait InstructionExtension: Sync {
     fn name(&self) -> &'static str;
 
     /// Check if this extension is enabled for the given configuration.
-    fn is_enabled(&self, extensions: Extensions) -> bool;
+    fn is_enabled(&self, extensions: &Extensions) -> bool;
 }
 
 // Standard RISC-V extension modules
-pub mod rva; // RVA - Atomic Instructions
-pub mod rvc; // RVC - Compressed Instructions
-pub mod rvd; // RVD - Double-Precision Floating-Point
-pub mod rvf; // RVF - Single-Precision Floating-Point
-pub mod rvi; // RV32I/RV64I - Base Integer Instruction Set
-pub mod rvm; // RVM - Multiply and Divide Instructions
+// RVA - Atomic Instructions
+// RVC - Compressed Instructions
+// RVD - Double-Precision Floating-Point
+// RVF - Single-Precision Floating-Point
+// RV32I/RV64I - Base Integer Instruction Set
+// RVM - Multiply and Divide Instructions
 
-// XuanTie vendor extension modules
-pub mod xtheadcondmov; // XTheadCondMov - Conditional Move Instructions
+// XuanTie custom extension modules
+// XTheadCondMov - Conditional Move Instructions
 
-use rva::RvaExtension;
-use rvc::RvcExtension;
-use rvd::RvdExtension;
-use rvf::RvfExtension;
-use rvi::RviExtension;
-use rvm::RvmExtension;
-use xtheadcondmov::XTheadCondMovExtension;
+use standard::{
+    RvaExtension, RvcExtension, RvdExtension, RvfExtension, RviExtension, RvmExtension,
+};
+use thead::CondMovExtension;
 
 /// Create all available standard RISC-V extensions.
 pub fn create_extensions() -> Vec<Box<dyn InstructionExtension>> {
@@ -112,6 +132,6 @@ pub fn create_extensions() -> Vec<Box<dyn InstructionExtension>> {
         Box::new(RvfExtension::new()),
         Box::new(RvdExtension::new()),
         Box::new(RvcExtension::new()),
-        Box::new(XTheadCondMovExtension::new()),
+        Box::new(CondMovExtension::new()),
     ]
 }

robustone-core/src/riscv/extensions/standard/mod.rs

@@ -0,0 +1,39 @@
+//! Standard RISC-V extensions and configuration.
+//!
+//! This module defines the `StandardExtensions` bitflags for core RISC-V
+//! extensions (I/M/A/F/D/C) and re-exports the corresponding extension
+//! handler types under the `standard` namespace.
+
+use bitflags::bitflags;
+
+pub mod rva;
+pub mod rvc;
+pub mod rvd;
+pub mod rvf;
+pub mod rvi;
+pub mod rvm;
+
+pub use rva::RvaExtension;
+pub use rvc::RvcExtension;
+pub use rvd::RvdExtension;
+pub use rvf::RvfExtension;
+pub use rvi::RviExtension;
+pub use rvm::RvmExtension;
+
+bitflags! {
+    /// Bitflags representing enabled standard RISC-V extensions.
+    pub struct StandardExtensions: u32 {
+        const I    = 1;
+        const M    = 1 << 1;
+        const A    = 1 << 2;
+        const F    = 1 << 3;
+        const D    = 1 << 4;
+        const C    = 1 << 5;
+        /// Shorthand for the standard G profile (IMAFD).
+        const G    = Self::I.bits()
+            | Self::M.bits()
+            | Self::A.bits()
+            | Self::F.bits()
+            | Self::D.bits();
+    }
+}

…bustone-core/src/riscv/extensions/rva.rs …ore/src/riscv/extensions/standard/rva.rsrobustone-core/src/riscv/extensions/rva.rs renamed to robustone-core/src/riscv/extensions/standard/rva.rs robustone-core/src/riscv/extensions/rva.rs renamed to robustone-core/src/riscv/extensions/standard/rva.rs

@@ -3,14 +3,15 @@
 //! This module implements the RISC-V atomic instructions extension (A extension),
 //! which provides atomic memory operations for synchronization and concurrency.
 
-use super::super::decoder::{RiscVDecodedInstruction, Xlen};
-use super::super::shared::{
+use super::StandardExtensions;
+use crate::error::DisasmError;
+use crate::riscv::decoder::{RiscVDecodedInstruction, Xlen};
+use crate::riscv::extensions::{Extensions, InstructionExtension};
+use crate::riscv::shared::{
     operands::convenience,
     registers::{RegisterManager, RegisterNameProvider},
 };
-use super::super::types::*;
-use super::{Extensions, InstructionExtension};
-use crate::error::DisasmError;
+use crate::riscv::types::*;
 
 /// RVA Atomic Instructions Extension
 pub struct RvaExtension {
@@ -115,9 +116,9 @@ impl InstructionExtension for RvaExtension {
         "A"
     }
 
-    fn is_enabled(&self, extensions: Extensions) -> bool {
+    fn is_enabled(&self, extensions: &Extensions) -> bool {
         // A extension bit (bit 2)
-        extensions.contains(Extensions::A)
+        extensions.standard.contains(StandardExtensions::A)
     }
 
     fn try_decode_standard(

…bustone-core/src/riscv/extensions/rvc.rs …ore/src/riscv/extensions/standard/rvc.rsrobustone-core/src/riscv/extensions/rvc.rs renamed to robustone-core/src/riscv/extensions/standard/rvc.rs robustone-core/src/riscv/extensions/rvc.rs renamed to robustone-core/src/riscv/extensions/standard/rvc.rs

@@ -3,15 +3,16 @@
 //! This module implements the RISC-V compressed instruction extension (C extension),
 //! which provides 16-bit compressed versions of common instructions to improve code density.
 
-use super::super::decoder::{RiscVDecodedInstruction, Xlen};
-use super::super::shared::{
+use super::StandardExtensions;
+use crate::error::DisasmError;
+use crate::riscv::decoder::{RiscVDecodedInstruction, Xlen};
+use crate::riscv::extensions::{Extensions, InstructionExtension};
+use crate::riscv::shared::{
     encoding::convenience as encoding_conv,
     operands::convenience,
     registers::{RegisterManager, RegisterNameProvider},
 };
-use super::super::types::*;
-use super::{Extensions, InstructionExtension};
-use crate::error::DisasmError;
+use crate::riscv::types::*;
 
 /// RVC Compressed Instructions Extension
 pub struct RvcExtension {
@@ -370,9 +371,9 @@ impl InstructionExtension for RvcExtension {
         "C"
     }
 
-    fn is_enabled(&self, extensions: Extensions) -> bool {
+    fn is_enabled(&self, extensions: &Extensions) -> bool {
         // C extension bit (bit 5)
-        extensions.contains(Extensions::C)
+        extensions.standard.contains(StandardExtensions::C)
     }
 
     fn try_decode_standard(

…bustone-core/src/riscv/extensions/rvd.rs …ore/src/riscv/extensions/standard/rvd.rsrobustone-core/src/riscv/extensions/rvd.rs renamed to robustone-core/src/riscv/extensions/standard/rvd.rs robustone-core/src/riscv/extensions/rvd.rs renamed to robustone-core/src/riscv/extensions/standard/rvd.rs

@@ -3,14 +3,15 @@
 //! This module implements the RISC-V double-precision floating-point extension (D extension),
 //! which provides IEEE 754 double-precision floating-point operations.
 
-use super::super::decoder::{RiscVDecodedInstruction, Xlen};
-use super::super::shared::{
+use super::StandardExtensions;
+use crate::error::DisasmError;
+use crate::riscv::decoder::{RiscVDecodedInstruction, Xlen};
+use crate::riscv::extensions::{Extensions, InstructionExtension};
+use crate::riscv::shared::{
     operands::convenience,
     registers::{RegisterManager, RegisterNameProvider},
 };
-use super::super::types::*;
-use super::{Extensions, InstructionExtension};
-use crate::error::DisasmError;
+use crate::riscv::types::*;
 
 /// RVD Double-Precision Floating-Point Extension
 pub struct RvdExtension {
@@ -175,9 +176,9 @@ impl InstructionExtension for RvdExtension {
         "D"
     }
 
-    fn is_enabled(&self, extensions: Extensions) -> bool {
+    fn is_enabled(&self, extensions: &Extensions) -> bool {
         // D extension bit (bit 4)
-        extensions.contains(Extensions::D)
+        extensions.standard.contains(StandardExtensions::D)
     }
 
     fn try_decode_standard(

…bustone-core/src/riscv/extensions/rvf.rs …ore/src/riscv/extensions/standard/rvf.rsrobustone-core/src/riscv/extensions/rvf.rs renamed to robustone-core/src/riscv/extensions/standard/rvf.rs robustone-core/src/riscv/extensions/rvf.rs renamed to robustone-core/src/riscv/extensions/standard/rvf.rs

@@ -3,14 +3,15 @@
 //! This module implements the RISC-V single-precision floating-point extension (F extension),
 //! which provides IEEE 754 single-precision floating-point operations.
 
-use super::super::decoder::{RiscVDecodedInstruction, Xlen};
-use super::super::shared::{
+use super::StandardExtensions;
+use crate::error::DisasmError;
+use crate::riscv::decoder::{RiscVDecodedInstruction, Xlen};
+use crate::riscv::extensions::{Extensions, InstructionExtension};
+use crate::riscv::shared::{
     operands::convenience,
     registers::{RegisterManager, RegisterNameProvider},
 };
-use super::super::types::*;
-use super::{Extensions, InstructionExtension};
-use crate::error::DisasmError;
+use crate::riscv::types::*;
 
 /// RVF Single-Precision Floating-Point Extension
 pub struct RvfExtension {
@@ -175,9 +176,9 @@ impl InstructionExtension for RvfExtension {
         "F"
     }
 
-    fn is_enabled(&self, extensions: Extensions) -> bool {
+    fn is_enabled(&self, extensions: &Extensions) -> bool {
         // F extension bit (bit 3)
-        extensions.contains(Extensions::F)
+        extensions.standard.contains(StandardExtensions::F)
     }
 
     fn try_decode_standard(