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35 | 35 | static int print_decimal(int v);
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36 | 36 | static int print_hex(int v);
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37 | 37 |
|
38 |
| -/* |
39 |
| - * This is an ungainly workaround (aka hack) basically I want to know |
40 |
| - * when the SPI port is 'done' sending all of the bits out, and it is |
41 |
| - * done when it has clocked enough bits that it would have received a |
42 |
| - * byte. Since we're using the SPI port in write_only mode I am not |
43 |
| - * collecting the "received" bytes into a buffer, but one could of |
44 |
| - * course. I keep track of how many bytes should have been returned |
45 |
| - * by decrementing the 'rx_pend' volatile. When it reaches 0 we know |
46 |
| - * we are done. |
47 |
| - */ |
48 |
| - |
49 |
| -volatile int rx_pend; |
50 |
| -volatile uint16_t spi_rx_buf; |
51 |
| - |
52 |
| -/* |
53 |
| - * This is the ISR we use. Note that the name is based on the name |
54 |
| - * in the irq.json file of libopencm3 plus the "_isr" extension. |
55 |
| - */ |
56 |
| -void |
57 |
| -spi5_isr(void) { |
58 |
| - spi_rx_buf = SPI_DR(SPI5); |
59 |
| - --rx_pend; |
60 |
| -} |
61 |
| - |
62 | 38 | /* Simple double buffering, one frame is displayed, the
|
63 | 39 | * other being built.
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64 | 40 | */
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@@ -343,10 +319,6 @@ lcd_spi_init(void) {
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343 | 319 | cur_frame = (uint16_t *)(SDRAM_BASE_ADDRESS);
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344 | 320 | display_frame = cur_frame + (LCD_WIDTH * LCD_HEIGHT);
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345 | 321 |
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346 |
| - rx_pend = 0; |
347 |
| - /* Implement state management hack */ |
348 |
| - // nvic_enable_irq(NVIC_SPI5_IRQ); |
349 |
| - |
350 | 322 | rcc_periph_clock_enable(RCC_SPI5);
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351 | 323 | spi_init_master(LCD_SPI, SPI_CR1_BAUDRATE_FPCLK_DIV_4,
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352 | 324 | SPI_CR1_CPOL_CLK_TO_0_WHEN_IDLE,
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|
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