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airliedairlied
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Merge tag 'amd-drm-fixes-6.11-2024-07-27' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.11-2024-07-27: amdgpu: - SMU 14.x update - Fix contiguous VRAM handling for IB parsing - GFX 12 fix - Regression fix for old APUs Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents 8400291 + d286008 commit 774c6f2

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9 files changed

+114
-19
lines changed

9 files changed

+114
-19
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1778,7 +1778,7 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
17781778
struct ttm_operation_ctx ctx = { false, false };
17791779
struct amdgpu_vm *vm = &fpriv->vm;
17801780
struct amdgpu_bo_va_mapping *mapping;
1781-
int r;
1781+
int i, r;
17821782

17831783
addr /= AMDGPU_GPU_PAGE_SIZE;
17841784

@@ -1793,13 +1793,13 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
17931793
if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->exec.ticket)
17941794
return -EINVAL;
17951795

1796-
if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1797-
(*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1798-
amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1799-
r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1800-
if (r)
1801-
return r;
1802-
}
1796+
(*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1797+
amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1798+
for (i = 0; i < (*bo)->placement.num_placement; i++)
1799+
(*bo)->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS;
1800+
r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1801+
if (r)
1802+
return r;
18031803

18041804
return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
18051805
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -103,7 +103,7 @@ static int amdgpu_mes_event_log_init(struct amdgpu_device *adev)
103103
if (!amdgpu_mes_log_enable)
104104
return 0;
105105

106-
r = amdgpu_bo_create_kernel(adev, AMDGPU_MES_LOG_BUFFER_SIZE, PAGE_SIZE,
106+
r = amdgpu_bo_create_kernel(adev, adev->mes.event_log_size, PAGE_SIZE,
107107
AMDGPU_GEM_DOMAIN_GTT,
108108
&adev->mes.event_log_gpu_obj,
109109
&adev->mes.event_log_gpu_addr,
@@ -113,7 +113,7 @@ static int amdgpu_mes_event_log_init(struct amdgpu_device *adev)
113113
return r;
114114
}
115115

116-
memset(adev->mes.event_log_cpu_addr, 0, PAGE_SIZE);
116+
memset(adev->mes.event_log_cpu_addr, 0, adev->mes.event_log_size);
117117

118118
return 0;
119119

@@ -1573,7 +1573,7 @@ static int amdgpu_debugfs_mes_event_log_show(struct seq_file *m, void *unused)
15731573
uint32_t *mem = (uint32_t *)(adev->mes.event_log_cpu_addr);
15741574

15751575
seq_hex_dump(m, "", DUMP_PREFIX_OFFSET, 32, 4,
1576-
mem, AMDGPU_MES_LOG_BUFFER_SIZE, false);
1576+
mem, adev->mes.event_log_size, false);
15771577

15781578
return 0;
15791579
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,6 @@ enum amdgpu_mes_priority_level {
5252

5353
#define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */
5454
#define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */
55-
#define AMDGPU_MES_LOG_BUFFER_SIZE 0x4000 /* Maximu log buffer size for MES */
5655

5756
struct amdgpu_mes_funcs;
5857

@@ -135,8 +134,9 @@ struct amdgpu_mes {
135134
unsigned long *doorbell_bitmap;
136135

137136
/* MES event log buffer */
138-
struct amdgpu_bo *event_log_gpu_obj;
139-
uint64_t event_log_gpu_addr;
137+
uint32_t event_log_size;
138+
struct amdgpu_bo *event_log_gpu_obj;
139+
uint64_t event_log_gpu_addr;
140140
void *event_log_cpu_addr;
141141

142142
/* ip specific functions */

‎drivers/gpu/drm/amd/amdgpu/mes_v11_0.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1163,6 +1163,8 @@ static int mes_v11_0_sw_init(void *handle)
11631163
adev->mes.kiq_hw_init = &mes_v11_0_kiq_hw_init;
11641164
adev->mes.kiq_hw_fini = &mes_v11_0_kiq_hw_fini;
11651165

1166+
adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE;
1167+
11661168
r = amdgpu_mes_init(adev);
11671169
if (r)
11681170
return r;

‎drivers/gpu/drm/amd/amdgpu/mes_v12_0.c

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -551,8 +551,10 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes)
551551
mes_set_hw_res_pkt.oversubscription_timer = 50;
552552
mes_set_hw_res_pkt.unmapped_doorbell_handling = 1;
553553

554-
mes_set_hw_res_pkt.enable_mes_event_int_logging = 0;
555-
mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr;
554+
if (amdgpu_mes_log_enable) {
555+
mes_set_hw_res_pkt.enable_mes_event_int_logging = 1;
556+
mes_set_hw_res_pkt.event_intr_history_gpu_mc_ptr = mes->event_log_gpu_addr;
557+
}
556558

557559
return mes_v12_0_submit_pkt_and_poll_completion(mes,
558560
&mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
@@ -1237,6 +1239,8 @@ static int mes_v12_0_sw_init(void *handle)
12371239
adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init;
12381240
adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini;
12391241

1242+
adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE;
1243+
12401244
r = amdgpu_mes_init(adev);
12411245
if (r)
12421246
return r;

‎drivers/gpu/drm/amd/include/mes_v11_api_def.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,9 @@
2828

2929
#define MES_API_VERSION 1
3030

31+
/* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG */
32+
#define AMDGPU_MES_LOG_BUFFER_SIZE 0x4000
33+
3134
/* Driver submits one API(cmd) as a single Frame and this command size is same
3235
* for all API to ease the debugging and parsing of ring buffer.
3336
*/

‎drivers/gpu/drm/amd/include/mes_v12_api_def.h

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,9 @@
2828

2929
#define MES_API_VERSION 0x14
3030

31+
/* Maximum log buffer size for MES. Needs to be updated if MES expands MES_EVT_INTR_HIST_LOG_12 */
32+
#define AMDGPU_MES_LOG_BUFFER_SIZE 0xC000
33+
3134
/* Driver submits one API(cmd) as a single Frame and this command size is same for all API
3235
* to ease the debugging and parsing of ring buffer.
3336
*/

‎drivers/gpu/drm/amd/pm/amdgpu_dpm.c

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -618,7 +618,8 @@ int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_versio
618618
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
619619
int r = 0;
620620

621-
if (!pp_funcs || !pp_funcs->load_firmware || adev->flags & AMD_IS_APU)
621+
if (!pp_funcs || !pp_funcs->load_firmware ||
622+
(is_support_sw_smu(adev) && (adev->flags & AMD_IS_APU)))
622623
return 0;
623624

624625
mutex_lock(&adev->pm.mutex);

‎drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c

Lines changed: 84 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -66,6 +66,7 @@
6666

6767
#define MP0_MP1_DATA_REGION_SIZE_COMBOPPTABLE 0x4000
6868
#define DEBUGSMC_MSG_Mode1Reset 2
69+
#define LINK_SPEED_MAX 3
6970

7071
static struct cmn2asic_msg_mapping smu_v14_0_2_message_map[SMU_MSG_MAX_COUNT] = {
7172
MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
@@ -221,7 +222,6 @@ static struct cmn2asic_mapping smu_v14_0_2_workload_map[PP_SMC_POWER_PROFILE_COU
221222
WORKLOAD_MAP(PP_SMC_POWER_PROFILE_WINDOW3D, WORKLOAD_PPLIB_WINDOW_3D_BIT),
222223
};
223224

224-
#if 0
225225
static const uint8_t smu_v14_0_2_throttler_map[] = {
226226
[THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
227227
[THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
@@ -241,7 +241,6 @@ static const uint8_t smu_v14_0_2_throttler_map[] = {
241241
[THROTTLER_GFX_APCC_PLUS_BIT] = (SMU_THROTTLER_APCC_BIT),
242242
[THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
243243
};
244-
#endif
245244

246245
static int
247246
smu_v14_0_2_get_allowed_feature_mask(struct smu_context *smu,
@@ -1869,6 +1868,88 @@ static ssize_t smu_v14_0_2_get_ecc_info(struct smu_context *smu,
18691868
return ret;
18701869
}
18711870

1871+
static ssize_t smu_v14_0_2_get_gpu_metrics(struct smu_context *smu,
1872+
void **table)
1873+
{
1874+
struct smu_table_context *smu_table = &smu->smu_table;
1875+
struct gpu_metrics_v1_3 *gpu_metrics =
1876+
(struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1877+
SmuMetricsExternal_t metrics_ext;
1878+
SmuMetrics_t *metrics = &metrics_ext.SmuMetrics;
1879+
int ret = 0;
1880+
1881+
ret = smu_cmn_get_metrics_table(smu,
1882+
&metrics_ext,
1883+
true);
1884+
if (ret)
1885+
return ret;
1886+
1887+
smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1888+
1889+
gpu_metrics->temperature_edge = metrics->AvgTemperature[TEMP_EDGE];
1890+
gpu_metrics->temperature_hotspot = metrics->AvgTemperature[TEMP_HOTSPOT];
1891+
gpu_metrics->temperature_mem = metrics->AvgTemperature[TEMP_MEM];
1892+
gpu_metrics->temperature_vrgfx = metrics->AvgTemperature[TEMP_VR_GFX];
1893+
gpu_metrics->temperature_vrsoc = metrics->AvgTemperature[TEMP_VR_SOC];
1894+
gpu_metrics->temperature_vrmem = max(metrics->AvgTemperature[TEMP_VR_MEM0],
1895+
metrics->AvgTemperature[TEMP_VR_MEM1]);
1896+
1897+
gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity;
1898+
gpu_metrics->average_umc_activity = metrics->AverageUclkActivity;
1899+
gpu_metrics->average_mm_activity = max(metrics->Vcn0ActivityPercentage,
1900+
metrics->Vcn1ActivityPercentage);
1901+
1902+
gpu_metrics->average_socket_power = metrics->AverageSocketPower;
1903+
gpu_metrics->energy_accumulator = metrics->EnergyAccumulator;
1904+
1905+
if (metrics->AverageGfxActivity <= SMU_14_0_2_BUSY_THRESHOLD)
1906+
gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPostDs;
1907+
else
1908+
gpu_metrics->average_gfxclk_frequency = metrics->AverageGfxclkFrequencyPreDs;
1909+
1910+
if (metrics->AverageUclkActivity <= SMU_14_0_2_BUSY_THRESHOLD)
1911+
gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPostDs;
1912+
else
1913+
gpu_metrics->average_uclk_frequency = metrics->AverageMemclkFrequencyPreDs;
1914+
1915+
gpu_metrics->average_vclk0_frequency = metrics->AverageVclk0Frequency;
1916+
gpu_metrics->average_dclk0_frequency = metrics->AverageDclk0Frequency;
1917+
gpu_metrics->average_vclk1_frequency = metrics->AverageVclk1Frequency;
1918+
gpu_metrics->average_dclk1_frequency = metrics->AverageDclk1Frequency;
1919+
1920+
gpu_metrics->current_gfxclk = gpu_metrics->average_gfxclk_frequency;
1921+
gpu_metrics->current_socclk = metrics->CurrClock[PPCLK_SOCCLK];
1922+
gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK];
1923+
gpu_metrics->current_vclk0 = metrics->CurrClock[PPCLK_VCLK_0];
1924+
gpu_metrics->current_dclk0 = metrics->CurrClock[PPCLK_DCLK_0];
1925+
gpu_metrics->current_vclk1 = metrics->CurrClock[PPCLK_VCLK_0];
1926+
gpu_metrics->current_dclk1 = metrics->CurrClock[PPCLK_DCLK_0];
1927+
1928+
gpu_metrics->throttle_status =
1929+
smu_v14_0_2_get_throttler_status(metrics);
1930+
gpu_metrics->indep_throttle_status =
1931+
smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
1932+
smu_v14_0_2_throttler_map);
1933+
1934+
gpu_metrics->current_fan_speed = metrics->AvgFanRpm;
1935+
1936+
gpu_metrics->pcie_link_width = metrics->PcieWidth;
1937+
if ((metrics->PcieRate - 1) > LINK_SPEED_MAX)
1938+
gpu_metrics->pcie_link_speed = pcie_gen_to_speed(1);
1939+
else
1940+
gpu_metrics->pcie_link_speed = pcie_gen_to_speed(metrics->PcieRate);
1941+
1942+
gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1943+
1944+
gpu_metrics->voltage_gfx = metrics->AvgVoltage[SVI_PLANE_VDD_GFX];
1945+
gpu_metrics->voltage_soc = metrics->AvgVoltage[SVI_PLANE_VDD_SOC];
1946+
gpu_metrics->voltage_mem = metrics->AvgVoltage[SVI_PLANE_VDDIO_MEM];
1947+
1948+
*table = (void *)gpu_metrics;
1949+
1950+
return sizeof(struct gpu_metrics_v1_3);
1951+
}
1952+
18721953
static const struct pptable_funcs smu_v14_0_2_ppt_funcs = {
18731954
.get_allowed_feature_mask = smu_v14_0_2_get_allowed_feature_mask,
18741955
.set_default_dpm_table = smu_v14_0_2_set_default_dpm_table,
@@ -1905,6 +1986,7 @@ static const struct pptable_funcs smu_v14_0_2_ppt_funcs = {
19051986
.enable_thermal_alert = smu_v14_0_enable_thermal_alert,
19061987
.disable_thermal_alert = smu_v14_0_disable_thermal_alert,
19071988
.notify_memory_pool_location = smu_v14_0_notify_memory_pool_location,
1989+
.get_gpu_metrics = smu_v14_0_2_get_gpu_metrics,
19081990
.set_soft_freq_limited_range = smu_v14_0_set_soft_freq_limited_range,
19091991
.init_pptable_microcode = smu_v14_0_init_pptable_microcode,
19101992
.populate_umd_state_clk = smu_v14_0_2_populate_umd_state_clk,

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