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Fix SNC state detection on non-SNC-capable platforms #304

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6a4d764
lib: Fix incorrect bitmask for MBM counter length
shenxiaochen Nov 10, 2025
c5cc545
lib: Add support for Hygon Platform QoS features
shenxiaochen Nov 7, 2025
90c603e
lib/python: Add support for Hygon Platform QoS features
shenxiaochen Nov 10, 2025
b981133
lib: Set fixed MBM counter length for Hygon
shenxiaochen Nov 10, 2025
e07514a
lib: Fix SNC state detection on non-SNC-capable platforms
shenxiaochen Dec 30, 2025
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4 changes: 2 additions & 2 deletions lib/api.c
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Original file line number Diff line number Diff line change
Expand Up @@ -212,7 +212,7 @@ api_init(int interface, enum pqos_vendor vendor)
api.l2ca_get = hw_l2ca_get;
api.l2ca_get_min_cbm_bits = hw_l2ca_get_min_cbm_bits;

if (vendor == PQOS_VENDOR_AMD) {
if (vendor == PQOS_VENDOR_AMD || vendor == PQOS_VENDOR_HYGON) {
api.mba_get = hw_mba_get_amd;
api.mba_set = hw_mba_set_amd;
} else {
Expand Down Expand Up @@ -245,7 +245,7 @@ api_init(int interface, enum pqos_vendor vendor)
api.l2ca_get = os_l2ca_get;
api.l2ca_get_min_cbm_bits = os_l2ca_get_min_cbm_bits;

if (vendor == PQOS_VENDOR_AMD) {
if (vendor == PQOS_VENDOR_AMD || vendor == PQOS_VENDOR_HYGON) {
api.mba_get = os_mba_get_amd;
api.mba_set = os_mba_set_amd;
} else {
Expand Down
3 changes: 2 additions & 1 deletion lib/cap.c
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Expand Up @@ -270,7 +270,8 @@ cap_mba_discover(struct pqos_cap_mba **r_cap,

switch (iface) {
case PQOS_INTER_MSR:
if (cpu->vendor == PQOS_VENDOR_AMD)
if (cpu->vendor == PQOS_VENDOR_AMD ||
cpu->vendor == PQOS_VENDOR_HYGON)
ret = amd_cap_mba_discover(cap, cpu);
else
ret = hw_cap_mba_discover(cap, cpu);
Expand Down
20 changes: 16 additions & 4 deletions lib/cpuinfo.c
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Original file line number Diff line number Diff line change
Expand Up @@ -266,8 +266,8 @@ nearest_pow2(const unsigned n)
/**
* @brief Discovers cache APICID structure information
*
* Uses CPUID leaf 0x4(or 0x8000001D for AMD) to find L3 and L2 cache
* APICID information.
* Uses CPUID leaf 0x4(or 0x8000001D for AMD and Hygon) to find L3 and
* L2 cache APICID information.
*
* Assumes apic->pkg_shift is already set, this is in case
* L3/LLC is not detected.
Expand Down Expand Up @@ -529,6 +529,10 @@ detect_vendor(void)
} else if (vendor.ebx == 0x68747541 && vendor.edx == 0x69746E65 &&
vendor.ecx == 0x444D4163) {
cpu_vendor = PQOS_VENDOR_AMD;
} else if (vendor.ebx == 0x6f677948 && vendor.edx == 0x6e65476e &&
vendor.ecx == 0x656e6975) {
/* Vendor ID: "HygonGenuine" */
cpu_vendor = PQOS_VENDOR_HYGON;
} else {
cpu_vendor = PQOS_VENDOR_UNKNOWN;
}
Expand Down Expand Up @@ -606,6 +610,11 @@ init_config(struct cpuinfo_config *config, enum pqos_vendor vendor)
config->mba_msr_reg = PQOS_MSR_MBA_MASK_START_AMD;
config->mba_default_val = PQOS_MBA_MAX_AMD;
config->smba_msr_reg = PQOS_MSR_SMBA_MASK_START_AMD;
} else if (vendor == PQOS_VENDOR_HYGON) {
config->cpuid_cache_leaf = 0x8000001D;
config->mba_max = PQOS_MBA_MAX_AMD;
config->mba_msr_reg = PQOS_MSR_MBA_MASK_START_AMD;
config->mba_default_val = PQOS_MBA_MAX_AMD;
} else {
LOG_ERROR("init_config: init failed!");
return -EFAULT;
Expand Down Expand Up @@ -663,8 +672,8 @@ cpuinfo_init(enum pqos_interface interface, struct pqos_cpuinfo **topology)

/*
* Update l3cat_id and mba_id. For Intel, CAT and MBA ids are
* initialized to socket id. AMD uses l3_id for both CAT and MBA
* ids. Right now, both these ids are same. This could change in
* initialized to socket id. AMD and Hygon use l3_id for both CAT and
* MBA ids. Right now, both these ids are same. This could change in
* the future.
*/
for (i = 0; i < m_cpu->num_cores; ++i) {
Expand All @@ -674,6 +683,9 @@ cpuinfo_init(enum pqos_interface interface, struct pqos_cpuinfo **topology)
info->l3cat_id = info->l3_id;
info->mba_id = info->l3_id;
info->smba_id = info->l3_id;
} else if (vendor == PQOS_VENDOR_HYGON) {
info->l3cat_id = info->l3_id;
info->mba_id = info->l3_id;
} else {
info->l3cat_id = info->socket;
info->mba_id = info->socket;
Expand Down
25 changes: 24 additions & 1 deletion lib/hw_cap.c
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Expand Up @@ -236,6 +236,19 @@ hw_cap_mon_snc_state(const struct pqos_cpuinfo *cpu,

if (numa_num < 0 || socket_num < 0)
return PQOS_RETVAL_ERROR;

/**
* On platforms that do not support Sub-NUMA Clustering (SNC)
* monitoring (e.g., AMD and Hygon platforms).
*
* Set snc_num = 1 and return early.
*/
if (cpu->vendor == PQOS_VENDOR_AMD ||
cpu->vendor == PQOS_VENDOR_HYGON) {
*snc_num = 1;
return PQOS_RETVAL_OK;
}

if (numa_num == 0 || socket_num == 0 || numa_num == socket_num) {
*snc_num = 1;
*snc_mode = PQOS_SNC_LOCAL;
Expand Down Expand Up @@ -436,7 +449,17 @@ hw_cap_mon_discover(struct pqos_cap_mon **r_mon, const struct pqos_cpuinfo *cpu)
{
const unsigned max_rmid = cpuid_0xf_1.ecx + 1;
const uint32_t scale_factor = cpuid_0xf_1.ebx;
const unsigned counter_length = (cpuid_0xf_1.eax & 0x7f) + 24;
unsigned counter_offset = cpuid_0xf_1.eax & 0xff;
unsigned counter_length = 24;

/**
* Hygon CPU doesn't support CPUID 0xF.[ECX=1]:EAX as offset
* from 24. It supports fixed counter length of 32 bits.
*/
if (!counter_offset && cpu->vendor == PQOS_VENDOR_HYGON)
counter_offset = 8;

counter_length += counter_offset;

if (cpuid_0xf_1.edx & PQOS_CPUID_MON_L3_OCCUP_BIT) {
int iordt =
Expand Down
6 changes: 4 additions & 2 deletions lib/pqos.h
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Original file line number Diff line number Diff line change
Expand Up @@ -392,7 +392,8 @@ struct pqos_cacheinfo {
enum pqos_vendor {
PQOS_VENDOR_UNKNOWN = 0, /**< UNKNOWN */
PQOS_VENDOR_INTEL = 1, /**< INTEL */
PQOS_VENDOR_AMD = 2 /**< AMD */
PQOS_VENDOR_AMD = 2, /**< AMD */
PQOS_VENDOR_HYGON = 3 /**< HYGON */
};

/**
Expand All @@ -402,7 +403,7 @@ struct pqos_cpuinfo {
unsigned mem_size; /**< byte size of the structure */
struct pqos_cacheinfo l2; /**< L2 cache information */
struct pqos_cacheinfo l3; /**< L3 cache information */
enum pqos_vendor vendor; /**< vendor Intel/AMD */
enum pqos_vendor vendor; /**< vendor Intel/AMD/Hygon */
unsigned num_cores; /**< number of cores in the system */
struct pqos_coreinfo cores[0];
};
Expand Down Expand Up @@ -1746,6 +1747,7 @@ int pqos_mba_ctrl_enabled(const struct pqos_cap *cap,
* @retval 0 if vendor unknown
* @return 1 if the vendor is Intel
* @return 2 if the vendor is AMD
* @return 3 if the vendor is Hygon
*/
enum pqos_vendor pqos_get_vendor(const struct pqos_cpuinfo *cpu);

Expand Down
2 changes: 2 additions & 0 deletions lib/python/pqos/cpuinfo.py
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Original file line number Diff line number Diff line change
Expand Up @@ -165,6 +165,8 @@ def get_vendor(self):
return "INTEL"
if vendor == CPqosCpuInfo.PQOS_VENDOR_AMD:
return "AMD"
if vendor == CPqosCpuInfo.PQOS_VENDOR_HYGON:
return "HYGON"

return "UNKNOWN"

Expand Down
1 change: 1 addition & 0 deletions lib/python/pqos/native_struct.py
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Expand Up @@ -238,6 +238,7 @@ class CPqosCpuInfo(ctypes.Structure):
PQOS_VENDOR_UNKNOWN = 0
PQOS_VENDOR_INTEL = 1
PQOS_VENDOR_AMD = 2
PQOS_VENDOR_HYGON = 3

_fields_ = [
("mem_size", ctypes.c_uint), # Byte size of the structure
Expand Down
9 changes: 6 additions & 3 deletions pqos/alloc.c
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Expand Up @@ -265,7 +265,8 @@ set_l3_cos(const unsigned class_id,

/* set new L3 class definition */
ret = pqos_l3ca_set(sock_ids[i], 1, &ca);
if (cpu->vendor == PQOS_VENDOR_AMD)
if (cpu->vendor == PQOS_VENDOR_AMD ||
cpu->vendor == PQOS_VENDOR_HYGON)
package = "Core Complex";
else
package = "SOCKET";
Expand Down Expand Up @@ -429,7 +430,8 @@ set_mba_cos(const unsigned class_id,
const char *package;
int ret = pqos_mba_set(sock_ids[i], 1, &mba, &actual);

if (cpu->vendor == PQOS_VENDOR_AMD) {
if (cpu->vendor == PQOS_VENDOR_AMD ||
cpu->vendor == PQOS_VENDOR_HYGON) {
package = "Core Complex";
unit = "";
} else {
Expand Down Expand Up @@ -1483,7 +1485,8 @@ print_per_socket_config(const struct pqos_capability *cap_l3ca,
available = "";
} else {
available = " available";
if (cpu_info->vendor == PQOS_VENDOR_AMD)
if (cpu_info->vendor == PQOS_VENDOR_AMD ||
cpu_info->vendor == PQOS_VENDOR_HYGON)
unit = "";
else
unit = "%";
Expand Down
18 changes: 12 additions & 6 deletions rdtset/rdt.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1443,7 +1443,8 @@ alloc_get_default_cos(struct pqos_l2ca *l2_def,
mba_def->ctrl = 1;
mba_def->mb_max = UINT32_MAX;
} else
mba_def->mb_max = (m_cpu->vendor == PQOS_VENDOR_AMD)
mba_def->mb_max = (m_cpu->vendor == PQOS_VENDOR_AMD ||
m_cpu->vendor == PQOS_VENDOR_HYGON)
? RDT_MAX_MBA_AMD
: RDT_MAX_MBA;
}
Expand Down Expand Up @@ -1543,7 +1544,8 @@ cfg_configure_cos(const struct pqos_l2ca *l2ca,
if (g_cfg.verbose) {
const char *package;

if (m_cpu->vendor == PQOS_VENDOR_AMD)
if (m_cpu->vendor == PQOS_VENDOR_AMD ||
m_cpu->vendor == PQOS_VENDOR_HYGON)
package = "Core Complex";
else
package = "SOCKET";
Expand Down Expand Up @@ -1611,8 +1613,10 @@ cfg_configure_cos(const struct pqos_l2ca *l2ca,
mba_requested = mba_defs;
else if (mba_sc_mode(&g_cfg)) {
mba_requested.mb_max =
(m_cpu->vendor == PQOS_VENDOR_AMD) ? RDT_MAX_MBA_AMD
: RDT_MAX_MBA;
(m_cpu->vendor == PQOS_VENDOR_AMD ||
m_cpu->vendor == PQOS_VENDOR_HYGON)
? RDT_MAX_MBA_AMD
: RDT_MAX_MBA;
mba_requested.ctrl = 0;
}

Expand All @@ -1634,7 +1638,8 @@ cfg_configure_cos(const struct pqos_l2ca *l2ca,
const char *unit;
const char *package;

if (m_cpu->vendor == PQOS_VENDOR_AMD) {
if (m_cpu->vendor == PQOS_VENDOR_AMD ||
m_cpu->vendor == PQOS_VENDOR_HYGON) {
package = "Core Complex";
unit = "";
} else {
Expand Down Expand Up @@ -1681,7 +1686,8 @@ cfg_configure_cos(const struct pqos_l2ca *l2ca,
const char *unit;
const char *package;

if (m_cpu->vendor == PQOS_VENDOR_AMD) {
if (m_cpu->vendor == PQOS_VENDOR_AMD ||
m_cpu->vendor == PQOS_VENDOR_HYGON) {
package = "Core Complex";
unit = "";
} else {
Expand Down