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[Autobackout][FunctionalRegression]Revert of change: af5f505: Add Lit tests for ScalarizeFunction pass
Current tests were only debug info. Created Lit test with proper checks. Created also opaque pointers versions, but pass not fully supports opaque pointers. The 'Requires: opaque-ptr-fix' was added.
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‎IGC/Compiler/tests/ScalarizeFunction/basic.ll‎

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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2022 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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;
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; RUN: igc_opt --igc-scalarize -S < %s | FileCheck %s
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; ------------------------------------------------
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; ScalarizeFunction
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; ------------------------------------------------
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define spir_kernel void @test_unary(<2 x float> %src1) {
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; CHECK-LABEL: @test_unary(
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; CHECK: [[SRC1_SCALAR:%.*]] = extractelement <2 x float> [[SRC1:%.*]], i32 0
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; CHECK: [[SRC1_SCALAR1:%.*]] = extractelement <2 x float> [[SRC1]], i32 1
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; CHECK: [[TMP1:%.*]] = alloca <2 x float>, align 4
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; CHECK: [[TMP2:%.*]] = fneg float [[SRC1_SCALAR]]
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; CHECK: [[TMP3:%.*]] = fneg float [[SRC1_SCALAR1]]
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; CHECK: [[ASSEMBLED_VECT:%.*]] = insertelement <2 x float> undef, float [[TMP2]], i32 0
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; CHECK: [[ASSEMBLED_VECT2:%.*]] = insertelement <2 x float> [[ASSEMBLED_VECT]], float [[TMP3]], i32 1
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; CHECK: store <2 x float> [[ASSEMBLED_VECT2]], <2 x float>* [[TMP1]], align 8
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; CHECK: ret void
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;
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%1 = alloca <2 x float>, align 4
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%2 = fneg <2 x float> %src1
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store <2 x float> %2, <2 x float>* %1, align 8
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ret void
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}
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define spir_kernel void @test_binary(<2 x i32> %src1, <2 x i32> %src2) {
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; CHECK-LABEL: @test_binary(
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; CHECK: [[SCALAR2:%.*]] = extractelement <2 x i32> [[SRC2:%.*]], i32 0
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; CHECK: [[SCALAR3:%.*]] = extractelement <2 x i32> [[SRC2]], i32 1
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; CHECK: [[SCALAR:%.*]] = extractelement <2 x i32> [[SRC1:%.*]], i32 0
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; CHECK: [[SCALAR1:%.*]] = extractelement <2 x i32> [[SRC1]], i32 1
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; CHECK: [[TMP1:%.*]] = alloca <2 x i32>, align 4
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; CHECK: [[TMP2:%.*]] = add i32 [[SCALAR]], [[SCALAR2]]
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; CHECK: [[TMP3:%.*]] = add i32 [[SCALAR1]], [[SCALAR3]]
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; CHECK: [[ASSEMBLED_VECT:%.*]] = insertelement <2 x i32> undef, i32 [[TMP2]], i32 0
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; CHECK: [[ASSEMBLED_VECT4:%.*]] = insertelement <2 x i32> [[ASSEMBLED_VECT]], i32 [[TMP3]], i32 1
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; CHECK: store <2 x i32> [[ASSEMBLED_VECT4]], <2 x i32>* [[TMP1]], align 8
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; CHECK: ret void
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;
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%1 = alloca <2 x i32>, align 4
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%2 = add <2 x i32> %src1, %src2
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store <2 x i32> %2, <2 x i32>* %1, align 8
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ret void
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}
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define spir_kernel void @test_cast(<2 x i32> %src1) {
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; CHECK-LABEL: @test_cast(
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; CHECK: [[SCALAR:%.*]] = extractelement <2 x i32> [[SRC1:%.*]], i32 0
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; CHECK: [[SCALAR1:%.*]] = extractelement <2 x i32> [[SRC1]], i32 1
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; CHECK: [[TMP1:%.*]] = alloca <2 x i64>, align 4
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; CHECK: [[TMP2:%.*]] = alloca <4 x i16>, align 4
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; CHECK: [[TMP3:%.*]] = sext i32 [[SCALAR]] to i64
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; CHECK: [[TMP4:%.*]] = sext i32 [[SCALAR1]] to i64
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; CHECK: [[ASSEMBLED_VECT:%.*]] = insertelement <2 x i64> undef, i64 [[TMP3]], i32 0
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; CHECK: [[ASSEMBLED_VECT2:%.*]] = insertelement <2 x i64> [[ASSEMBLED_VECT]], i64 [[TMP4]], i32 1
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; CHECK: [[TMP5:%.*]] = bitcast <2 x i32> [[SRC1]] to <4 x i16>
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; CHECK: store <2 x i64> [[ASSEMBLED_VECT2]], <2 x i64>* [[TMP1]], align 16
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; CHECK: store <4 x i16> [[TMP5]], <4 x i16>* [[TMP2]], align 8
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; CHECK: ret void
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;
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%1 = alloca <2 x i64>, align 4
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%2 = alloca <4 x i16>, align 4
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%3 = sext <2 x i32> %src1 to <2 x i64>
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%4 = bitcast <2 x i32> %src1 to <4 x i16>
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store <2 x i64> %3, <2 x i64>* %1, align 16
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store <4 x i16> %4, <4 x i16>* %2, align 8
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ret void
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}
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define spir_kernel void @test_cmp(<2 x i32> %src1, <2 x i32> %src2) {
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; CHECK-LABEL: @test_cmp(
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; CHECK: [[SCALAR2:%.*]] = extractelement <2 x i32> [[SRC2:%.*]], i32 0
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; CHECK: [[SCALAR3:%.*]] = extractelement <2 x i32> [[SRC2]], i32 1
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; CHECK: [[SCALAR:%.*]] = extractelement <2 x i32> [[SRC1:%.*]], i32 0
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; CHECK: [[SCALAR1:%.*]] = extractelement <2 x i32> [[SRC1]], i32 1
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; CHECK: [[TMP1:%.*]] = alloca <2 x i1>, align 4
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; CHECK: [[TMP2:%.*]] = icmp eq i32 [[SCALAR]], [[SCALAR2]]
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; CHECK: [[TMP3:%.*]] = icmp eq i32 [[SCALAR1]], [[SCALAR3]]
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; CHECK: [[ASSEMBLED_VECT:%.*]] = insertelement <2 x i1> undef, i1 [[TMP2]], i32 0
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; CHECK: [[ASSEMBLED_VECT4:%.*]] = insertelement <2 x i1> [[ASSEMBLED_VECT]], i1 [[TMP3]], i32 1
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; CHECK: store <2 x i1> [[ASSEMBLED_VECT4]], <2 x i1>* [[TMP1]], align 1
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; CHECK: ret void
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;
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%1 = alloca <2 x i1>, align 4
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%2 = icmp eq <2 x i32> %src1, %src2
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store <2 x i1> %2, <2 x i1>* %1, align 1
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ret void
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}
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define spir_kernel void @test_select(<2 x i32> %src1, <4 x i16> %src2, i1 %cond, <4 x i1> %vcond) {
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; CHECK-LABEL: @test_select(
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; CHECK: [[SCALAR6:%.*]] = extractelement <4 x i1> [[VCOND:%.*]], i32 0
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; CHECK: [[SCALAR7:%.*]] = extractelement <4 x i1> [[VCOND]], i32 1
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; CHECK: [[SCALAR8:%.*]] = extractelement <4 x i1> [[VCOND]], i32 2
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; CHECK: [[SCALAR9:%.*]] = extractelement <4 x i1> [[VCOND]], i32 3
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; CHECK: [[SCALAR2:%.*]] = extractelement <4 x i16> [[SRC2:%.*]], i32 0
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; CHECK: [[SCALAR3:%.*]] = extractelement <4 x i16> [[SRC2]], i32 1
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; CHECK: [[SCALAR4:%.*]] = extractelement <4 x i16> [[SRC2]], i32 2
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; CHECK: [[SCALAR5:%.*]] = extractelement <4 x i16> [[SRC2]], i32 3
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; CHECK: [[SCALAR:%.*]] = extractelement <2 x i32> [[SRC1:%.*]], i32 0
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; CHECK: [[SCALAR1:%.*]] = extractelement <2 x i32> [[SRC1]], i32 1
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; CHECK: [[TMP1:%.*]] = alloca <2 x i32>, align 4
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; CHECK: [[TMP2:%.*]] = alloca <4 x i16>, align 4
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; CHECK: [[TMP3:%.*]] = select i1 [[COND:%.*]], i32 [[SCALAR]], i32 42
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; CHECK: [[TMP4:%.*]] = select i1 [[COND]], i32 [[SCALAR1]], i32 13
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; CHECK: [[ASSEMBLED_VECT:%.*]] = insertelement <2 x i32> undef, i32 [[TMP3]], i32 0
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; CHECK: [[ASSEMBLED_VECT10:%.*]] = insertelement <2 x i32> [[ASSEMBLED_VECT]], i32 [[TMP4]], i32 1
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; CHECK: [[TMP5:%.*]] = select i1 [[SCALAR6]], i16 [[SCALAR2]], i16 1
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; CHECK: [[TMP6:%.*]] = select i1 [[SCALAR7]], i16 [[SCALAR3]], i16 2
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; CHECK: [[TMP7:%.*]] = select i1 [[SCALAR8]], i16 [[SCALAR4]], i16 3
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; CHECK: [[TMP8:%.*]] = select i1 [[SCALAR9]], i16 [[SCALAR5]], i16 4
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; CHECK: [[ASSEMBLED_VECT11:%.*]] = insertelement <4 x i16> undef, i16 [[TMP5]], i32 0
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; CHECK: [[ASSEMBLED_VECT12:%.*]] = insertelement <4 x i16> [[ASSEMBLED_VECT11]], i16 [[TMP6]], i32 1
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; CHECK: [[ASSEMBLED_VECT13:%.*]] = insertelement <4 x i16> [[ASSEMBLED_VECT12]], i16 [[TMP7]], i32 2
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; CHECK: [[ASSEMBLED_VECT14:%.*]] = insertelement <4 x i16> [[ASSEMBLED_VECT13]], i16 [[TMP8]], i32 3
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; CHECK: [[ASSEMBLED_VECT15:%.*]] = insertelement <4 x i16> undef, i16 [[SCALAR2]], i32 0
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; CHECK: [[ASSEMBLED_VECT16:%.*]] = insertelement <4 x i16> [[ASSEMBLED_VECT15]], i16 [[SCALAR3]], i32 1
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; CHECK: [[ASSEMBLED_VECT17:%.*]] = insertelement <4 x i16> [[ASSEMBLED_VECT16]], i16 [[SCALAR4]], i32 2
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; CHECK: [[ASSEMBLED_VECT18:%.*]] = insertelement <4 x i16> [[ASSEMBLED_VECT17]], i16 [[SCALAR5]], i32 3
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; CHECK: store <2 x i32> [[ASSEMBLED_VECT10]], <2 x i32>* [[TMP1]], align 8
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; CHECK: store <4 x i16> [[ASSEMBLED_VECT14]], <4 x i16>* [[TMP2]], align 8
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; CHECK: [[TMP9:%.*]] = bitcast <4 x i16> [[ASSEMBLED_VECT18]] to i64
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; CHECK: ret void
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;
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%1 = alloca <2 x i32>, align 4
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%2 = alloca <4 x i16>, align 4
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%3 = select i1 %cond, <2 x i32> %src1, <2 x i32> <i32 42, i32 13>
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%4 = select <4 x i1> %vcond, <4 x i16> %src2, <4 x i16> <i16 1, i16 2, i16 3, i16 4>
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%5 = select i1 %cond, <4 x i16> %src2, <4 x i16> %src2
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store <2 x i32> %3, <2 x i32>* %1, align 8
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store <4 x i16> %4, <4 x i16>* %2, align 8
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%6 = bitcast <4 x i16> %5 to i64
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ret void
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}

‎IGC/Compiler/tests/ScalarizeFunction/fneg_optnone.ll‎

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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2024 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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;
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; REQUIRES: llvm-14-plus
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; RUN: igc_opt %s -S -o - --igc-scalarize | FileCheck %s
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; Function Attrs: noinline optnone
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define void @test_fneg_optnone(<4 x float> %src, <3 x float> addrspace(1)* %out) #0 {
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; CHECK-LABEL: @test_fneg_optnone(
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;
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; CHECK: [[EE0:%.*]] = extractelement <4 x float> %src, i32 0
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; CHECK: [[EE1:%.*]] = extractelement <4 x float> %src, i32 1
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; CHECK: [[EE2:%.*]] = extractelement <4 x float> %src, i32 2
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; CHECK: [[EE3:%.*]] = extractelement <4 x float> %src, i32 3
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; CHECK: [[IE0:%.*]] = insertelement <3 x float> undef, float [[EE0]], i32 0
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; CHECK: [[IE1:%.*]] = insertelement <3 x float> [[IE0]], float [[EE1]], i32 1
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; CHECK: [[IE2:%.*]] = insertelement <3 x float> [[IE1]], float [[EE2]], i32 2
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; CHECK: [[FNEG:%.*]] = fneg <3 x float> [[IE2]]
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; CHECK: store <3 x float> [[FNEG]], <3 x float> addrspace(1)* %out, align 4
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; CHECK-NOT: fneg <3 x float> undef
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%1 = shufflevector <4 x float> %src, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
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%2 = fneg <3 x float> %1
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store <3 x float> %2, <3 x float> addrspace(1)* %out, align 4
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ret void
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}
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attributes #0 = { noinline optnone }

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