Fix and improve inline asm

If inline asm's operands are aliases, the current code generate a copy
if the operand is input; and does not handle aliased output operand.

When using copy, it is a little tricky whether to use NoMask or not,
especially for output operands. In addition, using inline asm is most
likely for performance and additional copies should be avoided as much
as possible.

This change fixes output alias operands and also removes copies by
generating visa alias decl with non-zero offset.

Author: jgu222

IGC/Compiler/CISACodeGen/CISABuilder.cpp

@@ -4774,11 +4774,45 @@ void CEncoder::GetVISAPredefinedVar(CVariable *pVar, PreDefined_Vars var) {
   pVar->visaGenVariable[0] = pAliasGenVar;
 }
 
-void CEncoder::CreateVISAVar(CVariable *var) {
+// UseAliasOffset is valid for alias var only. It is true only for
+// inline asm and this function will creates a GenVar with non-zero
+// alias offset.
+void CEncoder::CreateVISAVar(CVariable *var, bool UseAliasOffset) {
   IGC_ASSERT(nullptr != var);
 
   if (var->GetAlias() != NULL) {
     var->ResolveAlias();
+
+    // If UseAliasOffset = false, an alias CVariable reuses its root's
+    // genVar unless their types are different. When their types are
+    // different, a new genVar is needed for the alias, but the alias
+    // offset of the new genVar is always set to zero (as its alias
+    // offset has been converted into regno/subregno already in code
+    // emit).
+    //
+    // If UseAliasOffset = true, it is used for inline asm only. As an
+    // alias offset isn't converted into regno/subregno as regno/subregno
+    // are provided by users in inline asm string. We use an alias genVar
+    // with non-zero alias offset. (See EmitPass::EmitInlineAsm())
+    if (UseAliasOffset && var->GetAliasOffset() > 0) {
+      SAlias alias(var->GetAlias(), var->GetType(), var);
+      auto aliasPair = m_aliasesMap.insert(std::pair<SAlias, CVariable *>(alias, var));
+      if (aliasPair.second == false) {
+        for (uint i = 0; i < var->GetNumberInstance(); i++)
+          var->visaGenVariable[i] = aliasPair.first->second->visaGenVariable[i];
+      } else {
+        IGC_ASSERT_MESSAGE(var->GetType() != ISA_TYPE_BOOL, "boolean cannot have alias");
+        IGC_ASSERT((var->GetSize() + var->GetAliasOffset()) <= var->GetAlias()->GetSize());
+        uint16_t nbElement = var->GetNumberElement();
+        for (uint i = 0; i < var->GetNumberInstance(); i++) {
+          V(vKernel->CreateVISAGenVar(var->visaGenVariable[i], var->getVisaCString(), nbElement, var->GetType(),
+                                      GetVISAAlign(var->GetAlias()), var->GetAlias()->visaGenVariable[i],
+                                      var->GetAliasOffset()));
+        }
+      }
+      return;
+    }
+
     // In case the alias is an exact copy or just a sub variable just re-use the
     // variable
     if (var->GetAlias()->GetType() == var->GetType()) {

IGC/Compiler/CISACodeGen/CISABuilder.hpp

@@ -49,17 +49,32 @@ struct SModifier {
 struct SAlias {
   CVariable *m_rootVar;
   VISA_Type m_type;
-  SAlias(CVariable *var, VISA_Type type) : m_rootVar(var), m_type(type) {}
+  // If m_aliasVar != null, visa GenVar's alias offset must be set to
+  // m_aliasVar->aliasOffset, not zero.
+  CVariable *m_aliasVar;
+  SAlias(CVariable *var, VISA_Type type, CVariable *aliasVar = nullptr)
+      : m_rootVar(var), m_type(type), m_aliasVar(aliasVar) {}
 };
 
 struct SAliasMapInfo {
-  static inline SAlias getEmptyKey() { return SAlias(nullptr, ISA_TYPE_UD); }
-  static inline SAlias getTombstoneKey() { return SAlias(nullptr, ISA_TYPE_D); }
+  static inline SAlias getEmptyKey() { return SAlias(nullptr, ISA_TYPE_UD, nullptr); }
+  static inline SAlias getTombstoneKey() { return SAlias(nullptr, ISA_TYPE_D, nullptr); }
   static unsigned getHashValue(const SAlias &Val) {
-    return llvm::DenseMapInfo<CVariable *>::getHashValue(Val.m_rootVar) ^ Val.m_type;
+    unsigned ty = (unsigned)Val.m_type;
+    if (Val.m_aliasVar)
+      ty += 0x011000;
+    return llvm::DenseMapInfo<CVariable *>::getHashValue(Val.m_rootVar) ^ ty;
   }
   static bool isEqual(const SAlias &LHS, const SAlias &RHS) {
-    return LHS.m_rootVar == RHS.m_rootVar && LHS.m_type == RHS.m_type;
+    if (!LHS.m_aliasVar && !RHS.m_aliasVar) {
+      // common case
+      return LHS.m_rootVar == RHS.m_rootVar && LHS.m_type == RHS.m_type;
+    } else if (LHS.m_aliasVar && RHS.m_aliasVar) {
+      // inline asm only
+      return LHS.m_rootVar == RHS.m_rootVar && LHS.m_type == RHS.m_type &&
+             LHS.m_aliasVar->GetAliasOffset() == RHS.m_aliasVar->GetAliasOffset();
+    }
+    return false;
   }
 };
 
@@ -121,7 +136,7 @@ class CEncoder {
   void SetExternFunctionFlag();
 
   void GetVISAPredefinedVar(CVariable *pVar, PreDefined_Vars var);
-  void CreateVISAVar(CVariable *var);
+  void CreateVISAVar(CVariable *var, bool UseAliasOffset = false);
   void DeclareInput(CVariable *var, uint offset, uint instance);
   void DeclarePred(CVariable *var, uint offset);
   void MarkAsOutput(CVariable *var);

IGC/Compiler/CISACodeGen/CShader.cpp

@@ -3363,6 +3363,21 @@ CVariable *CShader::GetNewAlias(CVariable *var, uint16_t numInstances) {
   return alias;
 }
 
+CVariable *CShader::GetNewAliasWithAliasOffset(CVariable *var) {
+  IGC_ASSERT_MESSAGE(false == var->IsImmediate(), "Trying to create an alias of an immediate");
+  CVariable *rootVar = var->GetAlias();
+  uint32_t offset = var->GetAliasOffset();
+  IGC_ASSERT(rootVar && offset > 0);
+  uint32_t rootSize = rootVar->GetSize();
+  uint32_t eltSize = var->GetElemSize();
+  uint32_t varSize = (rootSize > offset) ? rootSize - offset : 0;
+  uint16_t nelts = varSize / eltSize;
+  IGC_ASSERT_MESSAGE(nelts > 0, "Error: CVar has zero size!");
+  CVariable *alias = new (Allocator) CVariable(rootVar, var->GetType(), offset, nelts, var->IsUniform());
+  encoder.CreateVISAVar(alias, true);
+  return alias;
+}
+
 // createAliasIfNeeded() returns the Var that is either BaseVar or
 // its alias of the same size.
 //

IGC/Compiler/CISACodeGen/EmitVISAPass.cpp

@@ -9201,22 +9201,23 @@ void EmitPass::EmitInlineAsm(llvm::CallInst *inst) {
       m_encoder->Push();
       opnds[i] = tempMov;
     }
-    // WA: If the operand is an alias of another variable but gets mapped to the
-    // same variable name, we have to copy the alias into another register. This
-    // is because regioning info is determined by the user, and two variables
-    // that share the base register but reference different regions are not
-    // distinguishable to the inline asm string parser. Thus, a variable
-    // pointing to a subregion needs to be copied first before being used as an
-    // inline asm input.
-    // TODO: To avoid the extra move, we need to be able to explicity define an
-    // alias variable with offset instead of a region within the base value.
-    else if (opVar->GetAlias() && opVar->GetAliasOffset() > 0 &&
-             m_encoder->GetVariableName(opVar) == m_encoder->GetVariableName(opVar->GetAlias())) {
-      CVariable *tempMov =
-          m_currShader->GetNewVariable(opVar->GetNumberElement(), opVar->GetType(), EALIGN_GRF, opVar->IsUniform(), "");
-      m_encoder->Copy(tempMov, opVar);
-      m_encoder->Push();
-      opnds[i] = tempMov;
+    // Handle an aliase var with non-zero alias offset
+    // For example,
+    //     d0 = call asm "mov (N1_NM, 16) %0<0,1)<2> %1(0,0)<4;1,0>", s0
+    //   where d0 and s0 are aliases to d and s, respectively. Assume their
+    //   offsets are at 32 and 64, so d0 = alias<d,32>, s0 = alias<s,64>.
+    //   It is converted to the following:
+    //     .decl d0 ...., alias<d, 32>
+    //     .decl s0 ...., alias<s, 64>
+    //      d0 = call asm "...", s0
+    // By default (non-inline-asm operands), alias vars do not generate
+    // .decl with non-zero alias offset as shown above, because IGC emit will
+    // translate alias offsets into regno/subregno for each operands. Here,
+    // operands in inline-asm are not changed, thus .decl with non-zero alias
+    // offset must be used.
+    else if (opVar->GetAlias() && opVar->GetAliasOffset() > 0) {
+      CVariable *aliasVar = m_currShader->GetNewAliasWithAliasOffset(opVar);
+      opnds[i] = aliasVar;
     }
   }
 

IGC/Compiler/CISACodeGen/ShaderCodeGen.hpp

@@ -185,6 +185,8 @@ class CShader {
   CVariable *GetNewAlias(CVariable *var, VISA_Type type, uint16_t offset, uint16_t numElements, bool uniform);
   // Create a multi-instance alias of a single-instance variable.
   CVariable *GetNewAlias(CVariable *var, uint16_t numInstances);
+  // Create an alias whose genVar has non-zero alias offset (for inline asm)
+  CVariable *GetNewAliasWithAliasOffset(CVariable *var);
 
   // If BaseVar's type matches V's, return BaseVar; otherwise, create an new
   // alias CVariable to BaseVar. The newly-created alias CVariable's size

IGC/ocloc_tests/features/inline_asm/inline_asm_alias_operands.cl

@@ -0,0 +1,80 @@
+/*========================== begin_copyright_notice ============================
+
+Copyright (C) 2024 Intel Corporation
+
+SPDX-License-Identifier: MIT
+
+============================= end_copyright_notice ===========================*/
+
+// REQUIRES: regkeys, pvc-supported
+// RUN: ocloc compile -file %s -options "-igc_opts 'DumpVISAASMToConsole=1'" -device pvc | FileCheck %s
+
+// This is to test the handling of alias operands used in inline asm. For each alias operands,
+// a vISA decl with non-zero alias offset shall be generated.
+
+// CHECK-LABEL: .kernel
+// CHECK: .decl [[ROOTVAR:.*]] v_type=G type=w num_elts=128 align=wordx32
+// CHECK: .decl [[V0:.*]] v_type=G type=w num_elts=96 align=wordx32 alias=<[[ROOTVAR]], 64>
+// CHECK: .decl [[V1:.*]] v_type=G type=w num_elts=64 align=wordx32 alias=<[[ROOTVAR]], 128>
+// CHECK: .decl [[V2:.*]] v_type=G type=w num_elts=32 align=wordx32 alias=<[[ROOTVAR]], 192>
+//
+// CHECK-LABEL: .function
+//
+// 1st inline asm
+//
+// CHECK-LABEL: lsc_load_block2d.ugm
+//
+// 2nd inline asm
+//
+// CHECK: mov (M1_NM, 16) [[ROOTVAR]](0,0)<2> [[T0:.*]](0,0)<4;1,0>
+// CHECK: mov (M1_NM, 16) [[ROOTVAR]](0,1)<2> [[T0]](0,1)<4;1,0>
+// CHECK: mov (M1_NM, 16) [[V0]](0,0)<2>      [[T0]](0,2)<4;1,0>
+// CHECK: mov (M1_NM, 16) [[V0]](0,1)<2>      [[T0]](0,3)<4;1,0>
+//
+// 3rd inline asm
+//
+// CHECK: mov (M1_NM, 16) [[V1]](0,0)<2> [[T1:.*]](0,0)<4;1,0>
+// CHECK: mov (M1_NM, 16) [[V1]](0,1)<2> [[T1]](0,1)<4;1,0>
+// CHECK: mov (M1_NM, 16) [[V2]](0,0)<2> [[T1]](0,2)<4;1,0>
+// CHECK: mov (M1_NM, 16) [[V2]](0,1)<2> [[T1]](0,3)<4;1,0>
+//
+// CHECK-LABEL: ret (M1, 1)
+
+__attribute__((convergent)) void __spirv_Subgroup2DBlockStoreINTEL(
+  int ElementSize, int BlockWidth, int BlockHeight, int BlockCount,
+  void *src_pointer, global const void *dst_base_pointer, int memory_width,
+  int memory_height, int memory_pitch, int2 coordinate);
+
+__attribute__((intel_reqd_sub_group_size(16)))
+kernel void test(global uchar *a, global ushort *b)
+{
+    uchar x[16];
+    ushort y[16];
+
+    __asm__ (
+        "lsc_load_block2d.ugm (M1, 1) %0:d8.16x16nt flat[%1,15,15,15,0,0]"
+        : "=rw"(*(uchar16 *)(&x[0]))
+        : "rw.u"(a)
+    );
+
+    __asm__ (
+      "mov (M1_NM, 16) %0(0,0)<2> %2(0,0)<4;1,0>\n"
+      "mov (M1_NM, 16) %0(0,1)<2> %2(0,1)<4;1,0>\n"
+      "mov (M1_NM, 16) %1(0,0)<2> %2(0,2)<4;1,0>\n"
+      "mov (M1_NM, 16) %1(0,1)<2> %2(0,3)<4;1,0>\n"
+      : "=rw"(*(ushort2 *)(&y[0])), "=rw"(*(ushort2 *)(&y[2]))
+      : "rw"(*(uchar4 *)(&x[0]))
+    );
+
+    __asm__ (
+      "mov (M1_NM, 16) %0(0,0)<2> %2(0,0)<4;1,0>\n"
+      "mov (M1_NM, 16) %0(0,1)<2> %2(0,1)<4;1,0>\n"
+      "mov (M1_NM, 16) %1(0,0)<2> %2(0,2)<4;1,0>\n"
+      "mov (M1_NM, 16) %1(0,1)<2> %2(0,3)<4;1,0>\n"
+      : "=rw"(*(ushort2 *)(&y[4])), "=rw"(*(ushort2 *)(&y[6]))
+      : "rw"(*(uchar4 *)(&x[4]))
+    );
+
+    int2 xy = 0;
+    __spirv_Subgroup2DBlockStoreINTEL(2, 16, 8, 1, &y[0], b, 16, 8, 16, xy);
+}