[LoadStoreToLLVM] Refactor the 2D block load lowering. #4615

chengjunlu · 2025-07-04T01:16:41Z

Refactor the 2D block IO lowering for regular pointer by using the linear layout.

chengjunlu · 2025-07-09T03:32:34Z

Need wait the relend of the block store code in PR #4646

third_party/intel/lib/TritonIntelGPUToLLVM/LoadStoreOpToLLVM.cpp

Copilot

Pull Request Overview

This PR refactors the 2D block load lowering implementation in the LoadStoreOpToLLVM pass by transitioning from a DPAS-specific approach to using linear layout. The refactoring simplifies the code structure while maintaining functionality for 2D block I/O operations.

Key changes include:

Replaced complex DPAS-specific calculations with linear layout-based tile size determination
Simplified load operation generation by using register mapping from linear layout
Streamlined the code flow and reduced complexity in the load conversion logic

Reviewed Changes

Copilot reviewed 2 out of 2 changed files in this pull request and generated 4 comments.

File	Description
LoadStoreOpToLLVM.cpp	Refactored 2D block load lowering to use linear layout instead of DPAS-specific logic
test_block_store.py	Updated test to include block load operations and verify their generation

Copilot · 2025-07-24T04:25:52Z

third_party/intel/lib/TritonIntelGPUToLLVM/LoadStoreOpToLLVM.cpp

+    auto [tileHeight, tileWidth, numPackedVals, vBlocks, rowDim, colDim,
+          regPackedBases] =


[nitpick] Using structured bindings with auto can make the code less readable when the types are not obvious. Consider using explicit variable declarations or adding a comment explaining what getBlockIOTileSize returns.

Suggested change

auto [tileHeight, tileWidth, numPackedVals, vBlocks, rowDim, colDim,

regPackedBases] =

int tileHeight, tileWidth, numPackedVals, vBlocks, rowDim, colDim;

std::vector<int> regPackedBases;

std::tie(tileHeight, tileWidth, numPackedVals, vBlocks, rowDim, colDim,

regPackedBases) =

Copilot · 2025-07-24T04:25:52Z

third_party/intel/lib/TritonIntelGPUToLLVM/LoadStoreOpToLLVM.cpp

+    unsigned totalBytesPerRowPerMatrix = tileWidth * packedElemSizeInBits / 8;
+    vBlocks = std::min(vBlocks, (int)(64 / totalBytesPerRowPerMatrix));
+    vBlocks = std::min(4, vBlocks);
+    // HW issue for vblock = 4


This comment is unclear and doesn't explain what the hardware issue is or why vBlocks is set to 1 when it equals 4. Consider adding more context about the specific hardware limitation.

Suggested change

// HW issue for vblock = 4

// Due to a hardware limitation, configurations where vBlocks equals 4

// are not supported. This issue arises because the hardware cannot handle

// 2D block loads or stores with this specific configuration. To work around

// this limitation, vBlocks is set to 1 when it equals 4.

Copilot · 2025-07-24T04:25:52Z

third_party/intel/lib/TritonIntelGPUToLLVM/LoadStoreOpToLLVM.cpp

+        unsigned opsPerChannel = dpasLayout.getOpsPerChannel();
+        if ((opsPerChannel == 4 && elemSizeInBits == 8) ||
+            (opsPerChannel == 2 && elemSizeInBits == 16)) {
+          // Use the VNNI packing format for DotOp B layout.


Remove commented-out code. If this assignment is needed for future reference, consider adding a TODO comment explaining why it's preserved.

Suggested change

// Use the VNNI packing format for DotOp B layout.

// Use the VNNI packing format for DotOp B layout.

// TODO: Retain this line for reference in case packedType needs to be explicitly set to i32_ty in future updates.

Copilot · 2025-07-24T04:25:52Z

third_party/intel/lib/TritonIntelGPUToLLVM/LoadStoreOpToLLVM.cpp

+        assert(maskElems.size() == otherElems.size() &&
+               "Invalid size of the masks.");


This assertion compares maskElems.size() with otherElems.size(), but otherElems may be empty when there's no 'other' value. This could cause a false assertion failure when mask is provided but other is not.

Suggested change

assert(maskElems.size() == otherElems.size() &&

"Invalid size of the masks.");

assert((otherElems.empty() || maskElems.size() == otherElems.size()) &&

"Invalid size of the masks: maskElems and otherElems sizes do not match.");

…or pointer. Signed-off-by: Lu,Chengjun <[email protected]>

anmyachev · 2025-08-29T12:21:47Z

Need wait the relend of the block store code in PR #4646

Hi @chengjunlu! It's not blocked anymore?

whitneywhtsang · 2025-08-29T12:24:27Z

Need wait the relend of the block store code in PR #4646

Hi @chengjunlu! It's not blocked anymore?

It is no longer blocked, I will help landing this PR.

chengjunlu force-pushed the chengjun/refactor_block_io_load branch from 5ac88f5 to 719c526 Compare July 9, 2025 03:31

chengjunlu force-pushed the chengjun/refactor_block_io_load branch from 719c526 to d725f19 Compare July 9, 2025 03:36

chengjunlu commented Jul 9, 2025

View reviewed changes

third_party/intel/lib/TritonIntelGPUToLLVM/LoadStoreOpToLLVM.cpp Outdated Show resolved Hide resolved

chengjunlu marked this pull request as draft July 9, 2025 07:29

chengjunlu force-pushed the chengjun/refactor_block_io_load branch 3 times, most recently from 5689429 to 3cce958 Compare July 24, 2025 03:28

chengjunlu marked this pull request as ready for review July 24, 2025 03:28

chengjunlu changed the title ~~[DRAFT] Refactor the 2D block load lowering.~~ [LoadStoreToLLVM] Refactor the 2D block load lowering. Jul 24, 2025

chengjunlu linked an issue Jul 24, 2025 that may be closed by this pull request

Replace the load op to llvm loop infrastructure with loops over linear layout input dimensions #3895

Open

chengjunlu mentioned this pull request Jul 24, 2025

Replace the load op to llvm loop infrastructure with loops over linear layout input dimensions #3895

Open

chengjunlu force-pushed the chengjun/refactor_block_io_load branch from 3cce958 to 9308fcf Compare July 24, 2025 04:24

chengjunlu requested review from Copilot, etiotto and whitneywhtsang July 24, 2025 04:24

Copilot AI reviewed Jul 24, 2025

View reviewed changes

chengjunlu force-pushed the chengjun/refactor_block_io_load branch 2 times, most recently from 689448e to a562276 Compare July 28, 2025 02:00

chengjunlu and others added 2 commits July 28, 2025 09:54

[LoadStoreOpToLLVM] Refactor block load lowering of tt.load with tens…

a562276

…or pointer. Signed-off-by: Lu,Chengjun <[email protected]>

Merge branch 'main' into chengjun/refactor_block_io_load

a262681

whitneywhtsang marked this pull request as draft October 16, 2025 00:34

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edited by etiotto

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		auto [tileHeight, tileWidth, numPackedVals, vBlocks, rowDim, colDim,
		regPackedBases] =

-    auto [tileHeight, tileWidth, numPackedVals, vBlocks, rowDim, colDim,
-          regPackedBases] =
+    int tileHeight, tileWidth, numPackedVals, vBlocks, rowDim, colDim;
+    std::vector<int> regPackedBases;
+    std::tie(tileHeight, tileWidth, numPackedVals, vBlocks, rowDim, colDim,
+             regPackedBases) =

-    // HW issue for vblock = 4
+    // Due to a hardware limitation, configurations where vBlocks equals 4
+    // are not supported. This issue arises because the hardware cannot handle
+    // 2D block loads or stores with this specific configuration. To work around
+    // this limitation, vBlocks is set to 1 when it equals 4.

	// Use the VNNI packing format for DotOp B layout.
	// Use the VNNI packing format for DotOp B layout.
	// TODO: Retain this line for reference in case packedType needs to be explicitly set to i32_ty in future updates.

		assert(maskElems.size() == otherElems.size() &&
		"Invalid size of the masks.");

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Pull Request Overview

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chengjunlu commented Jul 4, 2025 •

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chengjunlu commented Jul 9, 2025 •

edited by etiotto

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