crc: add RISC-V implementation

The CRC module of ISA-L has been accelerated using RISC-V's V, Zbc, Zvbc, and Zvbb instruction sets, implementing data folding and Barrett reduction optimizations.

Signed-off-by: Ji Dong <[email protected]>

Author: yinlenree

configure.ac

@@ -38,6 +38,9 @@ AM_CONDITIONAL([CPU_PPC64LE], [test "$CPU" = "ppc64le"])
 AM_CONDITIONAL([CPU_RISCV64], [test "$CPU" = "riscv64"])
 AM_CONDITIONAL([CPU_UNDEFINED], [test "x$CPU" = "x"])
 AM_CONDITIONAL([HAVE_RVV], [false])
+AM_CONDITIONAL([HAVE_ZBC], [false])
+AM_CONDITIONAL([HAVE_ZVBC], [false])
+AM_CONDITIONAL([HAVE_ZVBB], [false])
 
 # Check for programs
 AC_PROG_CC_STDC
@@ -57,7 +60,7 @@ case "${CPU}" in
 
 	riscv64)
 
-		AC_MSG_CHECKING([checking RVV support])
+		AC_MSG_CHECKING([RVV support])
 		AC_COMPILE_IFELSE(
 			[AC_LANG_PROGRAM([], [
 				__asm__ volatile(
@@ -70,11 +73,64 @@ case "${CPU}" in
 			[AC_DEFINE([HAVE_RVV], [0], [Disable RVV instructions])
 			AM_CONDITIONAL([HAVE_RVV], [false]) rvv=no]
 		)
+    AC_MSG_RESULT([$rvv])
+    AC_MSG_CHECKING([ZBC support])
+    AC_COMPILE_IFELSE(
+      [AC_LANG_PROGRAM([], [
+				__asm__ volatile(
+					".option arch, +zbc\n"
+					"clmul zero, zero, zero\n"
+          "clmulh zero, zero, zero\n"
+				);
+			])],
+			[AC_DEFINE([HAVE_ZBC], [1], [Enable ZBC instructions])
+			AM_CONDITIONAL([HAVE_ZBC], [true]) zbc=yes],
+			[AC_DEFINE([HAVE_ZBC], [0], [Disable ZBC instructions])
+			AM_CONDITIONAL([HAVE_ZBC], [false]) zbc=no]
+    )
+    AC_MSG_RESULT([$zbc])
+    AC_MSG_CHECKING([ZVBC support])
+    AC_COMPILE_IFELSE(
+      [AC_LANG_PROGRAM([], [
+				__asm__ volatile(
+					".option arch, +v, +zvbc\n"
+          "vsetivli zero, 2, e64, m1, ta, ma\n"
+          "vmv.s.x v0, zero\n"
+					"vclmul.vv v0, v0, v0\n"
+          "vclmulh.vv v0, v0, v0\n"
+				);
+			])],
+			[AC_DEFINE([HAVE_ZVBC], [1], [Enable ZVBC instructions])
+			AM_CONDITIONAL([HAVE_ZVBC], [true]) zvbc=yes],
+			[AC_DEFINE([HAVE_ZVBC], [0], [Disable ZVBC instructions])
+			AM_CONDITIONAL([HAVE_ZVBC], [false]) zvbc=no]
+    )
+    AC_MSG_RESULT([$zvbc])
+    AC_MSG_CHECKING([ZVBB support])
+    AC_COMPILE_IFELSE(
+      [AC_LANG_PROGRAM([], [
+				__asm__ volatile(
+					".option arch, +v, +zvbb\n"
+          "vsetivli zero, 2, e64, m1, ta, ma\n"
+          "vmv.s.x v0, zero\n"
+					"vrev8.v v0, v0\n"
+				);
+			])],
+			[AC_DEFINE([HAVE_ZVBB], [1], [Enable ZVBB instructions])
+			AM_CONDITIONAL([HAVE_ZVBB], [true]) zvbb=yes],
+			[AC_DEFINE([HAVE_ZVBB], [0], [Disable ZVBB instructions])
+			AM_CONDITIONAL([HAVE_ZVBB], [false]) zvbb=no]
+    )
 		if test "x$rvv" = "xyes"; then
-		  CFLAGS+=" -march=rv64gcv"
-		  CCASFLAGS+=" -march=rv64gcv"
-		fi
-		AC_MSG_RESULT([$rvv])
+      if test "x$zbc" = "xyes" && test "x$zvbc" = "xyes" && test "x$zvbb" = "xyes"; then
+          CFLAGS+=" -march=rv64gcv_zbc_zvbc_zvbb"
+          CCASFLAGS+=" -march=rv64gcv_zbc_zvbc_zvbb"
+      else
+          CFLAGS+=" -march=rv64gcv"
+          CCASFLAGS+=" -march=rv64gcv"
+      fi
+    fi
+		AC_MSG_RESULT([$zvbb])
 		;;
 
 	*)
@@ -239,4 +295,4 @@ AC_MSG_RESULT([
         ldflags:                ${LDFLAGS}
 
         debug:                  ${enable_debug}
-])
+])

crc/Makefile.am

@@ -28,14 +28,14 @@
 ########################################################################
 
 include crc/aarch64/Makefile.am
+include crc/riscv64/Makefile.am
 
 lsrc  += \
 	crc/crc_base.c \
 	crc/crc64_base.c
 
 lsrc_base_aliases += crc/crc_base_aliases.c
 lsrc_ppc64le      += crc/crc_base_aliases.c
-lsrc_riscv64      += crc/crc_base_aliases.c
 
 lsrc_x86_64 += \
 	crc/crc16_t10dif_01.asm \

crc/riscv64/Makefile.am

@@ -0,0 +1,46 @@
+########################################################################
+#  Copyright(c) 2025 ZTE Corporation All rights reserved.
+#
+#  Redistribution and use in source and binary forms, with or without
+#  modification, are permitted provided that the following conditions
+#  are met:
+#    * Redistributions of source code must retain the above copyright
+#      notice, this list of conditions and the following disclaimer.
+#    * Redistributions in binary form must reproduce the above copyright
+#      notice, this list of conditions and the following disclaimer in
+#      the documentation and/or other materials provided with the
+#      distribution.
+#    * Neither the name of ZTE Corporation nor the names of its
+#      contributors may be used to endorse or promote products derived
+#      from this software without specific prior written permission.
+#
+#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#########################################################################
+lsrc_riscv64 += \
+	crc/riscv64/crc_multibinary_riscv.S	\
+	crc/riscv64/crc_riscv64_dispatcher.c
+
+lsrc_riscv64 += \
+	crc/riscv64/crc16_t10dif_vclmul.S \
+	crc/riscv64/crc16_t10dif_copy_vclmul.S \
+	crc/riscv64/crc32_ieee_norm_vclmul.S \
+	crc/riscv64/crc32_iscsi_refl_vclmul.S \
+	crc/riscv64/crc32_gzip_refl_vclmul.S \
+	crc/riscv64/crc64_ecma_refl_vclmul.S \
+	crc/riscv64/crc64_ecma_norm_vclmul.S \
+	crc/riscv64/crc64_iso_refl_vclmul.S \
+	crc/riscv64/crc64_iso_norm_vclmul.S \
+	crc/riscv64/crc64_jones_refl_vclmul.S \
+	crc/riscv64/crc64_jones_norm_vclmul.S \
+	crc/riscv64/crc64_rocksoft_refl_vclmul.S \
+	crc/riscv64/crc64_rocksoft_norm_vclmul.S