Skip to content

Commit 1cee4fa

Browse files
mshockwavemichaelmaitland
mshockwave
and
michaelmaitland
authored
[RISCV] Update the vector integer division cycle in SiFive7 scheduling model (#159468)
Vector integer division in SiFive7 processes a single bit at a time up to 4 elements. This patch updates to reflect this behavior. Co-authored-by: Michael Maitland <[email protected]>
1 parent a3f901f commit 1cee4fa

14 files changed

+180
-177
lines changed

‎llvm/lib/Target/RISCV/RISCVSchedSiFive7.td‎

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -692,8 +692,11 @@ multiclass SiFive7WriteResBase<int VLEN,
692692

693693
foreach mx = SchedMxList in {
694694
foreach sew = SchedSEWSet<mx>.val in {
695-
defvar Cycles = !mul(SiFive7GetDivOrSqrtFactor<sew>.c,
696-
!div(SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c, 4));
695+
// One bit at a time, but up to four elements can be processed at a time.
696+
// Add 3 to number of elements to ensure the group formed by remainder
697+
// elements are accounted for.
698+
defvar Cycles =
699+
!mul(sew, !div(!add(3, SiFive7GetCyclesOnePerElement<mx, sew, VLEN>.c), 4));
697700
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
698701
let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
699702
defm : LMULSEWWriteResMXSEW<"WriteVIDivV", [VCQ, VA1], mx, sew, IsWorstCase>;

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX280/different-sew-instruments.s‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -11,13 +11,13 @@ vdiv.vv v8, v8, v12
1111

1212
# CHECK: Iterations: 1
1313
# CHECK-NEXT: Instructions: 4
14-
# CHECK-NEXT: Total Cycles: 359
14+
# CHECK-NEXT: Total Cycles: 261
1515
# CHECK-NEXT: Total uOps: 4
1616

1717
# CHECK: Dispatch Width: 2
18-
# CHECK-NEXT: uOps Per Cycle: 0.01
19-
# CHECK-NEXT: IPC: 0.01
20-
# CHECK-NEXT: Block RThroughput: 356.0
18+
# CHECK-NEXT: uOps Per Cycle: 0.02
19+
# CHECK-NEXT: IPC: 0.02
20+
# CHECK-NEXT: Block RThroughput: 258.0
2121

2222
# CHECK: Instruction Info:
2323
# CHECK-NEXT: [1]: #uOps
@@ -29,9 +29,9 @@ vdiv.vv v8, v8, v12
2929

3030
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
3131
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
32-
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
32+
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12
3333
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
34-
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
34+
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12
3535

3636
# CHECK: Resources:
3737
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
@@ -45,14 +45,14 @@ vdiv.vv v8, v8, v12
4545

4646
# CHECK: Resource pressure per iteration:
4747
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
48-
# CHECK-NEXT: - - 2.00 - 356.00 2.00 - -
48+
# CHECK-NEXT: - - 2.00 - 258.00 2.00 - -
4949

5050
# CHECK: Resource pressure by instruction:
5151
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
5252
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
53-
# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12
53+
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12
5454
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
55-
# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12
55+
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12
5656

5757
# CHECK: Timeline view:
5858
# CHECK-NEXT: Index 0123

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX280/fractional-lmul-data.s‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -11,13 +11,13 @@ vdiv.vv v12, v12, v12
1111

1212
# CHECK: Iterations: 1
1313
# CHECK-NEXT: Instructions: 4
14-
# CHECK-NEXT: Total Cycles: 91
14+
# CHECK-NEXT: Total Cycles: 85
1515
# CHECK-NEXT: Total uOps: 4
1616

1717
# CHECK: Dispatch Width: 2
18-
# CHECK-NEXT: uOps Per Cycle: 0.04
19-
# CHECK-NEXT: IPC: 0.04
20-
# CHECK-NEXT: Block RThroughput: 88.0
18+
# CHECK-NEXT: uOps Per Cycle: 0.05
19+
# CHECK-NEXT: IPC: 0.05
20+
# CHECK-NEXT: Block RThroughput: 82.0
2121

2222
# CHECK: Instruction Info:
2323
# CHECK-NEXT: [1]: #uOps
@@ -29,9 +29,9 @@ vdiv.vv v12, v12, v12
2929

3030
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
3131
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
32-
# CHECK-NEXT: 1 56 56.00 vdiv.vv v12, v12, v12
32+
# CHECK-NEXT: 1 64 64.00 vdiv.vv v12, v12, v12
3333
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
34-
# CHECK-NEXT: 1 30 30.00 vdiv.vv v12, v12, v12
34+
# CHECK-NEXT: 1 16 16.00 vdiv.vv v12, v12, v12
3535

3636
# CHECK: Resources:
3737
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
@@ -45,11 +45,11 @@ vdiv.vv v12, v12, v12
4545

4646
# CHECK: Resource pressure per iteration:
4747
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
48-
# CHECK-NEXT: - - 2.00 - 88.00 2.00 - -
48+
# CHECK-NEXT: - - 2.00 - 82.00 2.00 - -
4949

5050
# CHECK: Resource pressure by instruction:
5151
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
5252
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
53-
# CHECK-NEXT: - - - - 57.00 1.00 - - vdiv.vv v12, v12, v12
53+
# CHECK-NEXT: - - - - 65.00 1.00 - - vdiv.vv v12, v12, v12
5454
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
55-
# CHECK-NEXT: - - - - 31.00 1.00 - - vdiv.vv v12, v12, v12
55+
# CHECK-NEXT: - - - - 17.00 1.00 - - vdiv.vv v12, v12, v12

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX280/multiple-same-sew-instruments.s‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -16,13 +16,13 @@ vdivu.vv v8, v8, v12
1616

1717
# CHECK: Iterations: 1
1818
# CHECK-NEXT: Instructions: 8
19-
# CHECK-NEXT: Total Cycles: 574
19+
# CHECK-NEXT: Total Cycles: 648
2020
# CHECK-NEXT: Total uOps: 8
2121

2222
# CHECK: Dispatch Width: 2
2323
# CHECK-NEXT: uOps Per Cycle: 0.01
2424
# CHECK-NEXT: IPC: 0.01
25-
# CHECK-NEXT: Block RThroughput: 571.0
25+
# CHECK-NEXT: Block RThroughput: 645.0
2626

2727
# CHECK: Instruction Info:
2828
# CHECK-NEXT: [1]: #uOps
@@ -34,13 +34,13 @@ vdivu.vv v8, v8, v12
3434

3535
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
3636
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
37-
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
37+
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12
3838
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
39-
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
40-
# CHECK-NEXT: 1 114 114.00 vdivu.vv v8, v8, v12
39+
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12
40+
# CHECK-NEXT: 1 128 128.00 vdivu.vv v8, v8, v12
4141
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e32, m1, tu, mu
42-
# CHECK-NEXT: 1 112 112.00 vdiv.vv v8, v8, v12
43-
# CHECK-NEXT: 1 112 112.00 vdivu.vv v8, v8, v12
42+
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12
43+
# CHECK-NEXT: 1 128 128.00 vdivu.vv v8, v8, v12
4444

4545
# CHECK: Resources:
4646
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
@@ -54,18 +54,18 @@ vdivu.vv v8, v8, v12
5454

5555
# CHECK: Resource pressure per iteration:
5656
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
57-
# CHECK-NEXT: - - 3.00 - 571.00 5.00 - -
57+
# CHECK-NEXT: - - 3.00 - 645.00 5.00 - -
5858

5959
# CHECK: Resource pressure by instruction:
6060
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
6161
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
62-
# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12
62+
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12
6363
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
64-
# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12
65-
# CHECK-NEXT: - - - - 115.00 1.00 - - vdivu.vv v8, v8, v12
64+
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12
65+
# CHECK-NEXT: - - - - 129.00 1.00 - - vdivu.vv v8, v8, v12
6666
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e32, m1, tu, mu
67-
# CHECK-NEXT: - - - - 113.00 1.00 - - vdiv.vv v8, v8, v12
68-
# CHECK-NEXT: - - - - 113.00 1.00 - - vdivu.vv v8, v8, v12
67+
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12
68+
# CHECK-NEXT: - - - - 129.00 1.00 - - vdivu.vv v8, v8, v12
6969

7070
# CHECK: Timeline view:
7171
# CHECK-NEXT: Index 0123

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX280/needs-sew-but-only-lmul.s‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -10,13 +10,13 @@ vdiv.vv v8, v8, v12
1010

1111
# CHECK: Iterations: 1
1212
# CHECK-NEXT: Instructions: 3
13-
# CHECK-NEXT: Total Cycles: 485
13+
# CHECK-NEXT: Total Cycles: 261
1414
# CHECK-NEXT: Total uOps: 3
1515

1616
# CHECK: Dispatch Width: 2
1717
# CHECK-NEXT: uOps Per Cycle: 0.01
1818
# CHECK-NEXT: IPC: 0.01
19-
# CHECK-NEXT: Block RThroughput: 482.0
19+
# CHECK-NEXT: Block RThroughput: 258.0
2020

2121
# CHECK: Instruction Info:
2222
# CHECK-NEXT: [1]: #uOps
@@ -28,8 +28,8 @@ vdiv.vv v8, v8, v12
2828

2929
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
3030
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
31-
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
32-
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
31+
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12
32+
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12
3333

3434
# CHECK: Resources:
3535
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
@@ -43,13 +43,13 @@ vdiv.vv v8, v8, v12
4343

4444
# CHECK: Resource pressure per iteration:
4545
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
46-
# CHECK-NEXT: - - 1.00 - 482.00 2.00 - -
46+
# CHECK-NEXT: - - 1.00 - 258.00 2.00 - -
4747

4848
# CHECK: Resource pressure by instruction:
4949
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
5050
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
51-
# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12
52-
# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12
51+
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12
52+
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12
5353

5454
# CHECK: Timeline view:
5555
# CHECK-NEXT: Index 0123

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-at-start.s‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -8,13 +8,13 @@ vdiv.vv v8, v8, v12
88

99
# CHECK: Iterations: 1
1010
# CHECK-NEXT: Instructions: 2
11-
# CHECK-NEXT: Total Cycles: 244
11+
# CHECK-NEXT: Total Cycles: 132
1212
# CHECK-NEXT: Total uOps: 2
1313

1414
# CHECK: Dispatch Width: 2
15-
# CHECK-NEXT: uOps Per Cycle: 0.01
16-
# CHECK-NEXT: IPC: 0.01
17-
# CHECK-NEXT: Block RThroughput: 241.0
15+
# CHECK-NEXT: uOps Per Cycle: 0.02
16+
# CHECK-NEXT: IPC: 0.02
17+
# CHECK-NEXT: Block RThroughput: 129.0
1818

1919
# CHECK: Instruction Info:
2020
# CHECK-NEXT: [1]: #uOps
@@ -26,7 +26,7 @@ vdiv.vv v8, v8, v12
2626

2727
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
2828
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
29-
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
29+
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12
3030

3131
# CHECK: Resources:
3232
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
@@ -40,12 +40,12 @@ vdiv.vv v8, v8, v12
4040

4141
# CHECK: Resource pressure per iteration:
4242
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
43-
# CHECK-NEXT: - - 1.00 - 241.00 1.00 - -
43+
# CHECK-NEXT: - - 1.00 - 129.00 1.00 - -
4444

4545
# CHECK: Resource pressure by instruction:
4646
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
4747
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
48-
# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12
48+
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12
4949

5050
# CHECK: Timeline view:
5151
# CHECK-NEXT: Index 0123

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-in-middle.s‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -13,13 +13,13 @@ vdiv.vv v8, v8, v12
1313

1414
# CHECK: Iterations: 1
1515
# CHECK-NEXT: Instructions: 3
16-
# CHECK-NEXT: Total Cycles: 2834
16+
# CHECK-NEXT: Total Cycles: 2050
1717
# CHECK-NEXT: Total uOps: 3
1818

1919
# CHECK: Dispatch Width: 2
2020
# CHECK-NEXT: uOps Per Cycle: 0.00
2121
# CHECK-NEXT: IPC: 0.00
22-
# CHECK-NEXT: Block RThroughput: 2834.0
22+
# CHECK-NEXT: Block RThroughput: 2050.0
2323

2424
# CHECK: Instruction Info:
2525
# CHECK-NEXT: [1]: #uOps
@@ -30,9 +30,9 @@ vdiv.vv v8, v8, v12
3030
# CHECK-NEXT: [6]: HasSideEffects (U)
3131

3232
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
33-
# CHECK-NEXT: 1 1920 1920.00 vdiv.vv v8, v8, v12
33+
# CHECK-NEXT: 1 1024 1024.00 vdiv.vv v8, v8, v12
3434
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
35-
# CHECK-NEXT: 1 912 912.00 vdiv.vv v8, v8, v12
35+
# CHECK-NEXT: 1 1024 1024.00 vdiv.vv v8, v8, v12
3636

3737
# CHECK: Resources:
3838
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
@@ -46,13 +46,13 @@ vdiv.vv v8, v8, v12
4646

4747
# CHECK: Resource pressure per iteration:
4848
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
49-
# CHECK-NEXT: - - 1.00 - 2834.00 2.00 - -
49+
# CHECK-NEXT: - - 1.00 - 2050.00 2.00 - -
5050

5151
# CHECK: Resource pressure by instruction:
5252
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
53-
# CHECK-NEXT: - - - - 1921.00 1.00 - - vdiv.vv v8, v8, v12
53+
# CHECK-NEXT: - - - - 1025.00 1.00 - - vdiv.vv v8, v8, v12
5454
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
55-
# CHECK-NEXT: - - - - 913.00 1.00 - - vdiv.vv v8, v8, v12
55+
# CHECK-NEXT: - - - - 1025.00 1.00 - - vdiv.vv v8, v8, v12
5656

5757
# CHECK: Timeline view:
5858
# CHECK-NEXT: Index 0

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-in-region.s‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -12,13 +12,13 @@ vdiv.vv v8, v8, v12
1212

1313
# CHECK: Iterations: 1
1414
# CHECK-NEXT: Instructions: 2
15-
# CHECK-NEXT: Total Cycles: 118
15+
# CHECK-NEXT: Total Cycles: 132
1616
# CHECK-NEXT: Total uOps: 2
1717

1818
# CHECK: Dispatch Width: 2
1919
# CHECK-NEXT: uOps Per Cycle: 0.02
2020
# CHECK-NEXT: IPC: 0.02
21-
# CHECK-NEXT: Block RThroughput: 115.0
21+
# CHECK-NEXT: Block RThroughput: 129.0
2222

2323
# CHECK: Instruction Info:
2424
# CHECK-NEXT: [1]: #uOps
@@ -30,7 +30,7 @@ vdiv.vv v8, v8, v12
3030

3131
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
3232
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
33-
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
33+
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12
3434

3535
# CHECK: Resources:
3636
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
@@ -44,12 +44,12 @@ vdiv.vv v8, v8, v12
4444

4545
# CHECK: Resource pressure per iteration:
4646
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
47-
# CHECK-NEXT: - - 1.00 - 115.00 1.00 - -
47+
# CHECK-NEXT: - - 1.00 - 129.00 1.00 - -
4848

4949
# CHECK: Resource pressure by instruction:
5050
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
5151
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
52-
# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12
52+
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12
5353

5454
# CHECK: Timeline view:
5555
# CHECK-NEXT: Index 0123

‎llvm/test/tools/llvm-mca/RISCV/SiFiveX280/sew-instrument-straddles-region.s‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -13,13 +13,13 @@ vdiv.vv v8, v8, v12
1313

1414
# CHECK: Iterations: 1
1515
# CHECK-NEXT: Instructions: 2
16-
# CHECK-NEXT: Total Cycles: 118
16+
# CHECK-NEXT: Total Cycles: 132
1717
# CHECK-NEXT: Total uOps: 2
1818

1919
# CHECK: Dispatch Width: 2
2020
# CHECK-NEXT: uOps Per Cycle: 0.02
2121
# CHECK-NEXT: IPC: 0.02
22-
# CHECK-NEXT: Block RThroughput: 115.0
22+
# CHECK-NEXT: Block RThroughput: 129.0
2323

2424
# CHECK: Instruction Info:
2525
# CHECK-NEXT: [1]: #uOps
@@ -31,7 +31,7 @@ vdiv.vv v8, v8, v12
3131

3232
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
3333
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
34-
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
34+
# CHECK-NEXT: 1 128 128.00 vdiv.vv v8, v8, v12
3535

3636
# CHECK: Resources:
3737
# CHECK-NEXT: [0] - VLEN512SiFive7FDiv
@@ -45,12 +45,12 @@ vdiv.vv v8, v8, v12
4545

4646
# CHECK: Resource pressure per iteration:
4747
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
48-
# CHECK-NEXT: - - 1.00 - 115.00 1.00 - -
48+
# CHECK-NEXT: - - 1.00 - 129.00 1.00 - -
4949

5050
# CHECK: Resource pressure by instruction:
5151
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
5252
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
53-
# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12
53+
# CHECK-NEXT: - - - - 129.00 1.00 - - vdiv.vv v8, v8, v12
5454

5555
# CHECK: Timeline view:
5656
# CHECK-NEXT: Index 0123

0 commit comments

Comments
 (0)