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This change adds new supported targets, gfx941 and gfx942. It also fixes the supported subgroup size config value for AMD RDNA GPUs, due to the fact that the ROCm driver does not allow support for wave64 mode in HIP, for gfx10 and gx11 family of GPUs, which are based on the RDNA architecture. This is a result of wavefront/cross-lane functions that only work with wave32.

This change adds new supported targets, gfx941 and gfx942.
It also fixes the supported subgroup size config value for AMD RDNA GPUs, due
to the fact that the ROCm driver does not allow support for wave64 mode in HIP,
for gfx10 and gx11 family of GPUs, which are based on the RDNA architecture.
This is a result of wavefront/cross-lane functions that only work with wave32.
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GeorgeWeb commented Sep 17, 2024

Clang :: Driver/sycl.c

Failing clang test on Windows looks unrelated to this.

Update: Passing after rebase on latest.

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GeorgeWeb commented Sep 24, 2024

@intel/dpcpp-tools-reviewers This is not a high prio change by all means, so no rush. I am just pinging for reminder in case it may have been missed by any chance. Thanks!

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@intel/llvm-gatekeepers This looks ready to merge now. Thanks!

@ldrumm ldrumm merged commit 7f1ab96 into intel:sycl Oct 8, 2024
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4 participants