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merged 3 commits into from
Oct 11, 2024
Merged

[Driver][SYCL] Properly pass object contents with FPGA archives #15661

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5c23a27
[Driver][SYCL] Properly pass object contents with FPGA archives
mdtoguchi Oct 10, 2024
cd7b88b
Address review comments and clang-format
mdtoguchi Oct 10, 2024
2ca4093
Missed comment updates
mdtoguchi Oct 11, 2024
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26 changes: 24 additions & 2 deletions clang/lib/Driver/Driver.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7446,8 +7446,30 @@ void Driver::BuildActions(Compilation &C, DerivedArgList &Args,
if (Args.hasArg(options::OPT_fsycl_link_EQ) &&
Args.hasArg(options::OPT_fintelfpga)) {
// Wrap the object when creating an FPGA AOCX or AOCR binary.
auto *BC = C.MakeAction<OffloadWrapperJobAction>(LI, types::TY_LLVM_BC);
auto *ASM = C.MakeAction<BackendJobAction>(BC, types::TY_PP_Asm);
// When the input file is an AOCR (early) archive, the unbundled host
// binary consists of a list of objects. We cannot directly wrap that
// binary to be consumed later - this has to go through each listed
// object.
bool FPGAEarly = true;
if (auto *A = C.getInputArgs().getLastArg(options::OPT_fsycl_link_EQ))
FPGAEarly = A->getValue() == StringRef("early");

Action *WrapperAction;
if ((LI->getType() == types::TY_FPGA_AOCR ||
LI->getType() == types::TY_FPGA_AOCR_EMU) &&
!FPGAEarly) {
auto *RenameAction = C.MakeAction<FileTableTformJobAction>(
LI, types::TY_Tempfilelist, types::TY_Tempfilelist);
RenameAction->addRenameColumnTform(FileTableTformJobAction::COL_ZERO,
FileTableTformJobAction::COL_CODE);
ActionList WrapperItems({RenameAction});
WrapperAction = C.MakeAction<OffloadWrapperJobAction>(
WrapperItems, types::TY_LLVM_BC);
} else
WrapperAction =
C.MakeAction<OffloadWrapperJobAction>(LI, types::TY_LLVM_BC);
auto *ASM =
C.MakeAction<BackendJobAction>(WrapperAction, types::TY_PP_Asm);
auto *OBJ = C.MakeAction<AssembleJobAction>(ASM, types::TY_Object);
OffloadAction::HostDependence HDep(
*OBJ, *C.getSingleOffloadToolChain<Action::OFK_Host>(),
Expand Down
7 changes: 6 additions & 1 deletion clang/lib/Driver/ToolChains/Clang.cpp
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Expand Up @@ -10283,6 +10283,11 @@ void OffloadWrapper::ConstructJob(Compilation &C, const JobAction &JA,
CmdArgs.push_back(
TCArgs.MakeArgString(Twine("-target=") + Triple.getTriple()));

if (Inputs[0].getType() == types::TY_Tempfiletable ||
Inputs[0].getType() == types::TY_Tempfilelist)
// wrapper actual input files are passed via the batch job file table:
CmdArgs.push_back(C.getArgs().MakeArgString("-batch"));

// Add input.
assert(Inputs[0].isFilename() && "Invalid input.");
CmdArgs.push_back(TCArgs.MakeArgString(Inputs[0].getFilename()));
Expand Down Expand Up @@ -10320,7 +10325,7 @@ void OffloadWrapper::ConstructJob(Compilation &C, const JobAction &JA,

if (Inputs[I].getType() == types::TY_Tempfiletable ||
Inputs[I].getType() == types::TY_Tempfilelist)
// wrapper actual input files are passed via the batch job file table:
// Input files are passed via the batch job file table.
CmdArgs.push_back(C.getArgs().MakeArgString("-batch"));

// Add input.
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6 changes: 4 additions & 2 deletions clang/test/Driver/sycl-offload-intelfpga-emu.cpp
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Expand Up @@ -64,8 +64,10 @@
// RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK-LIB,CHK-FPGA-LINK-LIB-EARLY %s

// CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=ao" "-targets=sycl-fpga_aocr_emu-intel-unknown" "-input={{.*}}" "-check-section"
// CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=aoo" "-targets=host-x86_64-unknown-linux-gnu" "-input=[[INPUT:.+\.a]]" "-output=[[OUTPUT1:.+\.txt]]" "-unbundle"
// CHK-FPGA-LINK-LIB: clang-offload-wrapper{{.*}} "-host" "x86_64-unknown-linux-gnu" "-o" "[[WRAPPED_AOCR_LIST_BC:.+\.bc]]" "-kind=host" "-target=x86_64-unknown-linux-gnu" "[[OUTPUT1]]"
// CHK-FPGA-LINK-LIB-EARLY: clang-offload-bundler{{.*}} "-type=aoo" "-targets=host-x86_64-unknown-linux-gnu" "-input=[[INPUT:.+\.a]]" "-output=[[OUTPUT1:.+\.txt]]" "-unbundle"
// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-bundler{{.*}} "-type=aoo" "-targets=host-x86_64-unknown-linux-gnu" "-input=[[INPUT:.+\.a]]" "-output=[[BOUTPUT:.+\.txt]]" "-unbundle"
// CHK-FPGA-LINK-LIB-IMAGE: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[OUTPUT1:.+\.txt]]" "[[BOUTPUT]]"
// CHK-FPGA-LINK-LIB: clang-offload-wrapper{{.*}} "-host" "x86_64-unknown-linux-gnu" "-o" "[[WRAPPED_AOCR_LIST_BC:.+\.bc]]" "-kind=host" "-target=x86_64-unknown-linux-gnu" "-batch" "[[OUTPUT1]]"
// CHK-FPGA-LINK-LIB: clang{{.*}} "-o" "[[OUTPUT_O:.+\.o]]" "-x" "ir" "[[WRAPPED_AOCR_LIST_BC]]"
// CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=aocr" "-targets=sycl-fpga_aocr_emu-intel-unknown" "-input=[[INPUT]]" "-output=[[OUTPUT2:.+\.aocr]]" "-unbundle"
// CHK-FPGA-LINK-LIB-IMAGE: llvm-foreach{{.*}} "--out-ext=aocx" "--in-file-list=[[OUTPUT2]]" "--in-replace=[[OUTPUT2]]" "--out-file-list=[[OUTPUT3:.+\.aocx]]" "--out-replace=[[OUTPUT3]]" "--" "{{.*}}opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT2]]" "-ir=[[OUTPUT3]]" "--bo=-g"
Expand Down
6 changes: 4 additions & 2 deletions clang/test/Driver/sycl-offload-intelfpga-link.cpp
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Expand Up @@ -67,8 +67,10 @@
// RUN: | FileCheck -check-prefixes=CHK-FPGA-LINK-LIB,CHK-FPGA-LINK-LIB-EARLY %s
// CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=ao" "-targets=sycl-fpga_aocx-intel-unknown" "-input={{.*}}" "-check-section"
// CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=ao" "-targets=sycl-fpga_aocr-intel-unknown" "-input={{.*}}" "-check-section"
// CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=aoo" "-targets=host-x86_64-unknown-linux-gnu" "-input=[[INPUT:.+\.a]]" "-output=[[OUTPUT1:.+\.txt]]" "-unbundle"
// CHK-FPGA-LINK-LIB: clang-offload-wrapper{{.*}} "-host" "x86_64-unknown-linux-gnu" "-o" "[[WRAPPED_AOCR_LIST_BC:.+\.bc]]" "-kind=host" "-target=x86_64-unknown-linux-gnu" "[[OUTPUT1]]"
// CHK-FPGA-LINK-LIB-EARLY: clang-offload-bundler{{.*}} "-type=aoo" "-targets=host-x86_64-unknown-linux-gnu" "-input=[[INPUT:.+\.a]]" "-output=[[OUTPUT1:.+\.txt]]" "-unbundle"
// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-bundler{{.*}} "-type=aoo" "-targets=host-x86_64-unknown-linux-gnu" "-input=[[INPUT:.+\.a]]" "-output=[[BOUTPUT:.+\.txt]]" "-unbundle"
// CHK-FPGA-LINK-LIB-IMAGE: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[OUTPUT1:.+\.txt]]" "[[BOUTPUT]]"
// CHK-FPGA-LINK-LIB: clang-offload-wrapper{{.*}} "-host" "x86_64-unknown-linux-gnu" "-o" "[[WRAPPED_AOCR_LIST_BC:.+\.bc]]" "-kind=host" "-target=x86_64-unknown-linux-gnu" "-batch" "[[OUTPUT1]]"
// CHK-FPGA-LINK-LIB: clang{{.*}} "-o" "[[OUTPUT_O:.+\.o]]" "-x" "ir" "[[WRAPPED_AOCR_LIST_BC]]"
// CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=aocr" "-targets=sycl-fpga_aocr-intel-unknown" "-input=[[INPUT]]" "-output=[[OUTPUT2:.+\.aocr]]" "-unbundle"
// CHK-FPGA-LINK-LIB-IMAGE: llvm-foreach{{.*}} "--out-ext=aocx" "--in-file-list=[[OUTPUT2]]" "--in-replace=[[OUTPUT2]]" "--out-file-list=[[OUTPUT3:.+\.aocx]]" "--out-replace=[[OUTPUT3]]" "--out-increment=a.prj" "--" "{{.*}}aoc{{.*}}" "-o" "[[OUTPUT3]]" "[[OUTPUT2]]" "-sycl" "-output-report-folder=a.prj" "-g"
Expand Down
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