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merged 7 commits into from
Oct 24, 2024
Merged

[Driver][SYCL] Address issue with code splitting and FPGA Archives #15794

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a494866
[Driver][SYCL] Address issue with code splitting and FPGA Archives
mdtoguchi Oct 21, 2024
1b40ef2
Update xfail count test
mdtoguchi Oct 22, 2024
bf4613e
Merge remote-tracking branch 'intel_llvm/sycl' into fpga-multi-image-…
mdtoguchi Oct 23, 2024
3ae148e
Update xfail test (again, since it was updated and moved)
mdtoguchi Oct 23, 2024
1378478
Address a few review comments
mdtoguchi Oct 23, 2024
e12ef19
Add additional comment describing individual wrapping step.
mdtoguchi Oct 23, 2024
d9b86b1
Merge remote-tracking branch 'intel_llvm/sycl' into fpga-multi-image-…
mdtoguchi Oct 24, 2024
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9 changes: 9 additions & 0 deletions clang/include/clang/Driver/Action.h
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Original file line number Diff line number Diff line change
Expand Up @@ -698,6 +698,14 @@ class OffloadWrapperJobAction : public JobAction {
// Get the compilation step setting.
bool getCompileStep() const { return CompileStep; }

// Set the individual wrapping setting. This is used to tell the wrapper job
// action that the wrapping (and subsequent compile step) should be done
// with for-each instead of using -batch.
void setIndividualWrap(bool SetValue) { IndividualWrap = SetValue; }

// Get the individual wrapping setting.
bool getIndividualWrap() const { return IndividualWrap; }

// Set the offload kind for the current wrapping job action. Default usage
// is to use the kind of the current toolchain.
void setOffloadKind(OffloadKind SetKind) { Kind = SetKind; }
Expand All @@ -707,6 +715,7 @@ class OffloadWrapperJobAction : public JobAction {

private:
bool CompileStep = true;
bool IndividualWrap = false;
OffloadKind Kind = OFK_None;
};

Expand Down
18 changes: 14 additions & 4 deletions clang/lib/Driver/Driver.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5433,8 +5433,11 @@ class OffloadingActionBuilder final {
if (auto *OWA = dyn_cast<OffloadWrapperJobAction>(DeviceAction))
OWA->setOffloadKind(Action::OFK_Host);
Action *CompiledDeviceAction =
C.MakeAction<OffloadWrapperJobAction>(WrapperItems,
types::TY_Object);
C.MakeAction<OffloadWrapperJobAction>(FPGAAOTAction,
types::TY_Tempfilelist);
if (auto *OWA =
dyn_cast<OffloadWrapperJobAction>(CompiledDeviceAction))
OWA->setIndividualWrap(true);
addDeps(CompiledDeviceAction, TC, BoundArch);
}
addDeps(DeviceAction, TC, BoundArch);
Expand Down Expand Up @@ -5708,6 +5711,9 @@ class OffloadingActionBuilder final {
};

Action *ExtractIRFilesAction = createExtractIRFilesAction();
// Device binaries that are individually wrapped when creating an
// FPGA Archive.
ActionList FPGAArchiveWrapperInputs;

if (IsNVPTX || IsAMDGCN) {
JobAction *FinAction =
Expand Down Expand Up @@ -5793,6 +5799,7 @@ class OffloadingActionBuilder final {
FileTableTformJobAction::COL_CODE,
FileTableTformJobAction::COL_CODE);
WrapperInputs.push_back(ReplaceFilesAction);
FPGAArchiveWrapperInputs.push_back(BuildCodeAction);
}
if (SkipWrapper) {
// Wrapper step not requested.
Expand Down Expand Up @@ -5827,8 +5834,11 @@ class OffloadingActionBuilder final {
if (auto *OWA = dyn_cast<OffloadWrapperJobAction>(DeviceAction))
OWA->setOffloadKind(Action::OFK_Host);
Action *CompiledDeviceAction =
C.MakeAction<OffloadWrapperJobAction>(WrapperInputs,
types::TY_Object);
C.MakeAction<OffloadWrapperJobAction>(
FPGAArchiveWrapperInputs, types::TY_Tempfilelist);
if (auto *OWA =
dyn_cast<OffloadWrapperJobAction>(CompiledDeviceAction))
OWA->setIndividualWrap(true);
addDeps(CompiledDeviceAction, TC, nullptr);
}
addDeps(DeviceAction, TC, nullptr);
Expand Down
42 changes: 36 additions & 6 deletions clang/lib/Driver/ToolChains/Clang.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -10263,8 +10263,18 @@ void OffloadWrapper::ConstructJob(Compilation &C, const JobAction &JA,
const InputInfo &I = Inputs[0];
assert(I.isFilename() && "Invalid input.");

if (I.getType() == types::TY_Tempfiletable ||
I.getType() == types::TY_Tempfilelist || IsEmbeddedIR)
// TODO: The embedded compilation step after the wrapping step restricts
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@asudarsa asudarsa Oct 23, 2024

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Why is this a TODO? Is this not more of a restriction?

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@mdtoguchi mdtoguchi Oct 23, 2024

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It is a restriction - but in my opinion it would be best to pull the compile step out of the wrapping step which provides a cleaner picture of the toolchain. We shouldn't expect the wrapping step to do the compilation too (it isn't embedded for OpenMP)

// the ability to control the 'for each' methodology used when performing
// device code splitting. We set the individual wrap behavior when we know
// the wrapping and compile step should be done individually. Ideally this
// would be controlled at the JobAction creation, but we cannot do that
// until the compilation of the wrap is it's own JobAction.
bool IndividualWrapCompile = WrapperJob.getIndividualWrap();
const InputInfo TempOutput(types::TY_LLVM_BC, WrapperFileName,
WrapperFileName);
if (!IndividualWrapCompile &&
(I.getType() == types::TY_Tempfiletable ||
I.getType() == types::TY_Tempfilelist || IsEmbeddedIR))
// Input files are passed via the batch job file table.
WrapperArgs.push_back(C.getArgs().MakeArgString("-batch"));
WrapperArgs.push_back(C.getArgs().MakeArgString(I.getFilename()));
Expand All @@ -10273,7 +10283,17 @@ void OffloadWrapper::ConstructJob(Compilation &C, const JobAction &JA,
JA, *this, ResponseFileSupport::None(),
TCArgs.MakeArgString(getToolChain().GetProgramPath(getShortName())),
WrapperArgs, std::nullopt);
C.addCommand(std::move(Cmd));

if (IndividualWrapCompile) {
// When wrapping FPGA device binaries for FPGA archives, create individual
// wrapped and compiled entries for the archive.
StringRef ParallelJobs =
C.getArgs().getLastArgValue(options::OPT_fsycl_max_parallel_jobs_EQ);
clang::driver::tools::SYCL::constructLLVMForeachCommand(
C, JA, std::move(Cmd), Inputs, TempOutput, this, "", "bc",
ParallelJobs);
} else
C.addCommand(std::move(Cmd));

if (WrapperCompileEnabled) {
// TODO Use TC.SelectTool().
Expand All @@ -10296,9 +10316,19 @@ void OffloadWrapper::ConstructJob(Compilation &C, const JobAction &JA,
SmallString<128> ClangPath(C.getDriver().Dir);
llvm::sys::path::append(ClangPath, "clang");
const char *Clang = C.getArgs().MakeArgString(ClangPath);
C.addCommand(std::make_unique<Command>(JA, *this,
ResponseFileSupport::None(), Clang,
ClangArgs, std::nullopt));
auto Cmd =
std::make_unique<Command>(JA, *this, ResponseFileSupport::None(),
Clang, ClangArgs, std::nullopt);
if (IndividualWrapCompile) {
StringRef ParallelJobs = C.getArgs().getLastArgValue(
options::OPT_fsycl_max_parallel_jobs_EQ);
InputInfoList Inputs;
Inputs.push_back(TempOutput);
clang::driver::tools::SYCL::constructLLVMForeachCommand(
C, JA, std::move(Cmd), Inputs, Output, this, "", "bc",
ParallelJobs);
} else
C.addCommand(std::move(Cmd));
}
return;
} // end of SYCL flavor of offload wrapper command creation
Expand Down
45 changes: 24 additions & 21 deletions clang/test/Driver/sycl-offload-intelfpga-emu.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -21,14 +21,17 @@
// CHK-FPGA-LINK: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.txt]]" "-spirv-max-version={{.*}}"{{.*}} "[[TABLEOUT]]"
// CHK-FPGA-EARLY: opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT3]]" "-ir=[[OUTPUT4:.+\.aocr]]" "--bo=-g"
// CHK-FPGA-IMAGE: opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT3]]" "-ir=[[OUTPUT4:.+\.aocx]]" "--bo=-g"
// CHK-FPGA-LINK: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" {{.*}} "-kind=sycl" "[[OUTPUT4]]"
// CHK-FPGA-LINK: clang{{.*}} "-c" "-o" "[[OBJOUTDEV:.+\.txt]]" "[[WRAPOUT]]"
// CHK-FPGA-LINK: file-table-tform{{.*}} "-replace=Code,Code" "-o" "[[TABLEOUT2:.+\.table]]" "[[OUTPUT2]]" "[[OUTPUT4]]"
// CHK-FPGA-LINK: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" {{.*}} "-kind=sycl" "-batch" "[[TABLEOUT2]]"
// CHK-FPGA-LINK: clang{{.*}} "-c" "-o" "[[OBJOUTDEV:.+\.o]]" "[[WRAPOUT]]"
// CHK-FPGA-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPPEROUT_O:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "-target=fpga_aocr_emu-intel-unknown" "-kind=sycl" "-batch" "[[TABLEOUT2]]"
// CHK-FPGA-EARLY: clang-offload-wrapper{{.*}} "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocr_emu-intel-unknown" "-kind=host" "[[WRAPPEROUT_O]]"
// CHK-FPGA-EARLY: clang{{.*}} "-c" "-o" "[[WRAPWRAPOUT:.+\.o]]"
// CHK-FPGA-EARLY: llvm-ar{{.*}} "cqL" "libfoo.a" "[[OBJOUT]]" "@[[OBJOUTDEV]]" "[[WRAPWRAPOUT]]"
// CHK-FPGA-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPPEROUT_O:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "--emit-reg-funcs=0" "-target=fpga_aocx-intel-unknown" "-kind=sycl" "-batch" "[[TABLEOUT2]]"
// CHK-FPGA-IMAGE: clang-offload-wrapper{{.*}} "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocx-intel-unknown" "-kind=host" "[[WRAPPEROUT_O]]"
// CHK-FPGA-IMAGE: clang{{.*}} "-c" "-o" "[[WRAPWRAPOUT:.+\.o]]"
// CHK-FPGA-EARLY: llvm-ar{{.*}} "cqL" "libfoo.a" "[[OBJOUT]]" "[[OBJOUTDEV]]"
// CHK-FPGA-IMAGE: llvm-ar{{.*}} "cqL" "libfoo.a" "[[OBJOUT]]"{{.*}} "[[WRAPWRAPOUT]]"
// CHK-FPGA-IMAGE: llvm-ar{{.*}} "cqL" "libfoo.a" "[[OBJOUT]]" "@[[OBJOUTDEV]]" "[[WRAPWRAPOUT]]"

/// -fintelfpga -fsycl-link clang-cl specific
// RUN: touch %t.obj
Expand All @@ -45,10 +48,13 @@
// CHK-FPGA-LINK-WIN: file-table-tform{{.*}} "-o" "[[TABLEOUT:.+\.txt]]" "[[OUTPUT2]]"
// CHK-FPGA-LINK-WIN: llvm-spirv{{.*}} "-o" "[[OUTPUT3:.+\.txt]]" "-spirv-max-version={{.*}}"{{.*}} "[[TABLEOUT]]"
// CHK-FPGA-LINK-WIN: opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT3]]" "-ir=[[OUTPUT4:.+\.aocr]]" "--bo=-g"
// CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-kind=sycl" "[[OUTPUT4]]"
// CHK-FPGA-LINK-WIN: clang{{.*}} "-c" "-o" "[[OBJOUTDEV:.+\.txt]]" "[[WRAPOUT]]"
// CHK-FPGA-LINK-WIN: file-table-tform{{.*}} "-replace=Code,Code" "-o" "[[TABLEOUT2:.+\.table]]" "[[OUTPUT2]]" "[[OUTPUT4]]"
// CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" {{.*}} "-kind=sycl" "-batch" "[[TABLEOUT2]]"
// CHK-FPGA-LINK-WIN: clang{{.*}} "-c" "-o" "[[OBJOUTDEV:.+\.obj]]" "[[WRAPOUT]]"
// CHK-FPGA-LINK-WIN: lib.exe{{.*}} "[[OBJOUT]]" "[[OBJOUTDEV]]" {{.*}} "-OUT:libfoo.lib"
// CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT2:.+\.obj]]" {{.*}} "-kind=sycl" "-batch" "[[TABLEOUT2]]"
// CHK-FPGA-LINK-WIN: clang-offload-wrapper{{.*}} "-o=[[WRAPWRAPOUT:.+\.bc]]" {{.*}} "-kind=host" "[[WRAPOUT2]]"
// CHK-FPGA-LINK-WIN: clang{{.*}} "-c" "-o" "[[OUTDEV:.+\.obj]]" "[[WRAPWRAPOUT]]"
// CHK-FPGA-LINK-WIN: lib.exe{{.*}} "[[OBJOUT]]" "@[[OBJOUTDEV]]" "[[OUTDEV]]" {{.*}} "-OUT:libfoo.lib"

/// Check -fintelfpga -fsycl-link with an FPGA archive
// Create the dummy archive
Expand All @@ -71,26 +77,23 @@
// CHK-FPGA-LINK-LIB: clang{{.*}} "-o" "[[OUTPUT_O:.+\.o]]" "-x" "ir" "[[WRAPPED_AOCR_LIST_BC]]"
// CHK-FPGA-LINK-LIB: clang-offload-bundler{{.*}} "-type=aocr" "-targets=sycl-fpga_aocr_emu-intel-unknown" "-input=[[INPUT]]" "-output=[[OUTPUT2:.+\.aocr]]" "-unbundle"
// CHK-FPGA-LINK-LIB-IMAGE: llvm-foreach{{.*}} "--out-ext=aocx" "--in-file-list=[[OUTPUT2]]" "--in-replace=[[OUTPUT2]]" "--out-file-list=[[OUTPUT3:.+\.aocx]]" "--out-replace=[[OUTPUT3]]" "--" "{{.*}}opencl-aot{{.*}} "-device=fpga_fast_emu" "-spv=[[OUTPUT2]]" "-ir=[[OUTPUT3]]" "--bo=-g"
// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPOUT:.+\.bc]]" "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocx-intel-unknown" "-kind=sycl" "[[OUTPUT3]]"
// CHK-FPGA-LINK-LIB-IMAGE: clang{{.*}} "-c"{{.*}} "[[WRAPOUT]]"
// CHK-FPGA-LINK-LIB-IMAGE: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[OUTPUT4:.+\.txt]]" "[[OUTPUT3]]"
// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-bundler{{.*}} "-type=aoo" "-targets=host-fpga_aocr_emu-intel-unknown" "-input=[[INPUT]]" "-output=[[OUTPUT_BUNDLE_BC:.+\.txt]]" "-unbundle"
// CHK-FPGA-LINK-LIB-IMAGE: file-table-tform{{.*}} "-rename=0,SymAndProps" "-o" "[[OUTPUT_BC2:.+\.txt]]" "[[OUTPUT_BUNDLE_BC]]"
// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "--emit-reg-funcs=0" "-target=fpga_aocx-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]"
// CHK-FPGA-LINK-LIB-IMAGE: clang{{.*}} "-c"{{.*}} "[[WRAPPED_SYM_PROP]]"
// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP2:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "--emit-reg-funcs=0" "-target=fpga_aocx-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]"
// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPWRAP_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocx-intel-unknown" "-kind=host" "[[WRAPPED_SYM_PROP2]]"
// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "--emit-reg-funcs=0" "-target=fpga_aocx-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]"
// CHK-FPGA-LINK-LIB-IMAGE: clang-offload-wrapper{{.*}} "-o=[[WRAPWRAP_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocx-intel-unknown" "-kind=host" "[[WRAPPED_SYM_PROP]]"
// CHK-FPGA-LINK-LIB-IMAGE: clang{{.*}} "-c"{{.*}} "[[WRAPWRAP_SYM_PROP]]"
// CHK-FPGA-LINK-LIB-EARLY: llvm-foreach{{.*}} "--out-ext=aocr" "--in-file-list=[[OUTPUT2]]" "--in-replace=[[OUTPUT2]]" "--out-file-list=[[OUTPUT3:.+\.aocr]]" "--out-replace=[[OUTPUT3]]" "--" "{{.*}}opencl-aot{{.*}}" "-device=fpga_fast_emu" "-spv=[[OUTPUT2]]" "-ir=[[OUTPUT3]]" "--bo=-g"
// CHK-FPGA-LINK-LIB-EARLY: file-table-tform{{.*}} "-rename=0,Code" "-o" "[[OUTPUT4:.+\.txt]]" "[[OUTPUT3]]"
// CHK-FPGA-LINK-LIB-EARLY: clang-offload-bundler{{.*}} "-type=aoo" "-targets=host-fpga_aocr_emu-intel-unknown" "-input=[[INPUT]]" "-output=[[OUTPUT_BUNDLE_BC:.+\.txt]]" "-unbundle"
// CHK-FPGA-LINK-LIB-EARLY: file-table-tform{{.*}} "-rename=0,SymAndProps" "-o" "[[OUTPUT_BC2:.+\.txt]]" "[[OUTPUT_BUNDLE_BC]]"
// CHK-FPGA-LINK-LIB-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu" "-target=fpga_aocr_emu-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]"
// CHK-FPGA-LINK-LIB-EARLY: clang{{.*}} "-c"{{.*}} "[[WRAPPED_SYM_PROP]]"
// CHK-FPGA-LINK-LIB-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP2:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "-target=fpga_aocr_emu-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]"
// CHK-FPGA-LINK-LIB-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPWRAP_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocr_emu-intel-unknown" "-kind=host" "[[WRAPPED_SYM_PROP2]]"
// CHK-FPGA-LINK-LIB-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPPED_SYM_PROP:.+\.o]]" "-host=x86_64-unknown-linux-gnu" "-target=fpga_aocr_emu-intel-unknown" "-kind=sycl" "--sym-prop-bc-files=[[OUTPUT_BC2]]" "-batch" "[[OUTPUT4]]"
// CHK-FPGA-LINK-LIB-EARLY: clang-offload-wrapper{{.*}} "-o=[[WRAPWRAP_SYM_PROP:.+\.bc]]" "-host=x86_64-unknown-linux-gnu"{{.*}} "-target=fpga_aocr_emu-intel-unknown" "-kind=host" "[[WRAPPED_SYM_PROP]]"
// CHK-FPGA-LINK-LIB-EARLY: clang{{.*}} "-c"{{.*}} "[[WRAPWRAP_SYM_PROP]]"
// CHK-FPGA-LINK-LIB: llvm-ar{{.*}} "cqL" {{.*}} "[[OUTPUT_O]]"


/// Check the warning's emission for conflicting emulation/hardware
// RUN: touch %t-aocr.a
// RUN: %clangxx -fintelfpga -fsycl-link=image -target x86_64-unknown-linux-gnu %t-aocr.a %s -Xshardware -### 2>&1 \
Expand Down Expand Up @@ -240,13 +243,13 @@
// CHK-FPGA-LINK-SRC: 15: file-table-tform, {14}, tempfilelist, (device-sycl)
// CHK-FPGA-LINK-SRC: 16: llvm-spirv, {15}, tempfilelist, (device-sycl)
// CHK-FPGA-LINK-SRC: 17: backend-compiler, {16}, fpga_aocr_emu, (device-sycl)
// CHK-FPGA-LINK-SRC: 18: file-table-tform, {14, 17}, tempfiletable, (device-sycl)
// CHK-FPGA-LINK-SRC: 19: clang-offload-wrapper, {18}, object, (device-sycl)
// CHK-FPGA-LINK-SRC: 20: offload, "device-sycl (spir64_fpga-unknown-unknown)" {19}, object
// CHK-FPGA-LINK-SRC: 21: clang-offload-wrapper, {18}, object, (device-sycl)
// CHK-FPGA-LINK-SRC: 18: clang-offload-wrapper, {17}, tempfilelist, (device-sycl)
// CHK-FPGA-LINK-SRC: 19: offload, "device-sycl (spir64_fpga-unknown-unknown)" {18}, tempfilelist
// CHK-FPGA-LINK-SRC: 20: file-table-tform, {14, 17}, tempfiletable, (device-sycl)
// CHK-FPGA-LINK-SRC: 21: clang-offload-wrapper, {20}, object, (device-sycl)
// CHK-FPGA-LINK-SRC: 22: clang-offload-wrapper, {21}, object, (device-sycl)
// CHK-FPGA-LINK-SRC: 23: offload, "device-sycl (spir64_fpga-unknown-unknown)" {22}, object
// CHK-FPGA-LINK-SRC: 24: linker, {12, 20, 23}, archive, (host-sycl)
// CHK-FPGA-LINK-SRC: 24: linker, {12, 19, 23}, archive, (host-sycl)

/// Check for implied options with emulation (-g -O0)
// RUN: %clang -### -target x86_64-unknown-linux-gnu -fintelfpga -g -O0 -Xs "-DFOO1 -DFOO2" %s 2>&1 \
Expand Down
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