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@RossBrunton
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@RossBrunton
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@intel/llvm-gatekeepers Please merge.

@dm-vodopyanov dm-vodopyanov merged commit 28ed9ff into intel:sycl Aug 27, 2025
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@dm-vodopyanov
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Does this feature have tests?

@RossBrunton
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@dm-vodopyanov This is covered under existing tests in the UR CTS and causes a lot of them to pass now. Offload is currently experimental and so currently isn't tested in CI and has never passed every test.

UR CTS Pass rate before (on my system):

Total Discovered Tests: 4685
  Skipped: 2146 (45.81%)
  Passed : 1305 (27.85%)
  Failed : 1234 (26.34%)

UR CTS Pass rate after:

Total Discovered Tests: 4712
  Skipped: 2152 (45.67%)
  Passed : 2266 (48.09%)
  Failed :  294 (6.24%)

@aelovikov-intel
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What we do in SYCL (e.g. for new hardware or for SPIR-V backend), is we introduce a new "feature" in the lit.cfg.py, markup existing tests with XFAIL/UNSUPPORTED: that-new-feature and add a run with that into CI. Can the same be done for UR?

@RossBrunton
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@aelovikov-intel We have a mechanism to do that in the UR CTS, but we haven't done it with the offload adapter yet.

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4 participants