Push 2025 05 05

.gitignore

@@ -32,4 +32,5 @@ latex/
 .vs/
 .idea/
 build
-src/simdjson
+src/simdjson
+.vscode/

pcm.spec

@@ -72,7 +72,6 @@ rm -rf $RPM_BUILD_ROOT
 %{_sbindir}/pcm-core
 %{_sbindir}/pcm-iio
 %{_sbindir}/pcm-latency
-%{_sbindir}/pcm-lspci
 %{_sbindir}/pcm-memory
 %{_sbindir}/pcm-msr
 %{_sbindir}/pcm-mmio

src/CMakeLists.txt

@@ -4,7 +4,7 @@
 include(FindOpenSSL)
 
 # All pcm-* executables
-set(PROJECT_NAMES pcm pcm-numa pcm-latency pcm-power pcm-msr pcm-memory pcm-tsx pcm-pcie pcm-core pcm-iio pcm-lspci pcm-pcicfg pcm-mmio pcm-tpmi pcm-raw pcm-accel)
+set(PROJECT_NAMES pcm pcm-numa pcm-latency pcm-power pcm-msr pcm-memory pcm-tsx pcm-pcie pcm-core pcm-iio pcm-pcicfg pcm-mmio pcm-tpmi pcm-raw pcm-accel)
 
 set(MINIMUM_OPENSSL_VERSION 1.1.1)
 

src/MacMSRDriver/PcmMsr/PcmMsr.cpp

@@ -64,10 +64,13 @@ void cpuGetTopoData(void* pTopos){
     uint32 smtMaskWidth = 0;
     uint32 coreMaskWidth = 0;
     uint32 l2CacheMaskShift = 0;
-    initCoreMasks(smtMaskWidth, coreMaskWidth, l2CacheMaskShift);
+    uint32 l3CacheMaskShift = 0;
+    initCoreMasks(smtMaskWidth, coreMaskWidth, l2CacheMaskShift, l3CacheMaskShift);
     PCM_CPUID_INFO cpuid_args;
     pcm_cpuid(0xb, 0x0, cpuid_args);
-    fillEntry(entry, smtMaskWidth, coreMaskWidth, l2CacheMaskShift, cpuid_args.array[3]);
+    const auto apic_id = cpuid_args.array[3];
+    fillEntry(entry, smtMaskWidth, coreMaskWidth, l2CacheMaskShift, apic_id);
+    entry.l3_cache_id = extract_bits_32(apic_id, l3CacheMaskShift, 31);
 }
 
 OSDefineMetaClassAndStructors(com_intel_driver_PcmMsr, IOService)

src/cpucounters.cpp

@@ -1101,6 +1101,7 @@ bool PCM::discoverSystemTopology()
     uint32 smtMaskWidth = 0;
     uint32 coreMaskWidth = 0;
     uint32 l2CacheMaskShift = 0;
+    uint32 l3CacheMaskShift = 0;
 
     struct domain
     {
@@ -1111,7 +1112,7 @@ bool PCM::discoverSystemTopology()
     {
         TemporalThreadAffinity aff0(0);
 
-        if (initCoreMasks(smtMaskWidth, coreMaskWidth, l2CacheMaskShift) == false)
+        if (initCoreMasks(smtMaskWidth, coreMaskWidth, l2CacheMaskShift, l3CacheMaskShift) == false)
         {
             std::cerr << "ERROR: Major problem? No leaf 0 under cpuid function 11.\n";
             return false;
@@ -1151,20 +1152,18 @@ bool PCM::discoverSystemTopology()
             for (size_t l = 0; l < topologyDomains.size(); ++l)
             {
                 topologyDomainMap[topologyDomains[l].type] = topologyDomains[l];
-#if 0
-                std::cerr << "Topology level: " << l <<
-                                      " type: " << topologyDomains[l].type <<
-                                      " (" << TopologyEntry::getDomainTypeStr(topologyDomains[l].type) << ")" <<
-                                      " width: " << topologyDomains[l].width <<
-                                      " levelShift: " << topologyDomains[l].levelShift <<
-                                      " nextLevelShift: " << topologyDomains[l].nextLevelShift << "\n";
-#endif
+                DBG(1 , "Topology level: " , l ,
+                                      " type: " , topologyDomains[l].type ,
+                                      " (" , TopologyEntry::getDomainTypeStr(topologyDomains[l].type) , ")" ,
+                                      " width: " , topologyDomains[l].width ,
+                                      " levelShift: " , topologyDomains[l].levelShift ,
+                                      " nextLevelShift: " , topologyDomains[l].nextLevelShift);
             }
         }
     }
 
 #ifndef __APPLE__
-    auto populateEntry = [&topologyDomainMap,&smtMaskWidth, &coreMaskWidth, &l2CacheMaskShift](TopologyEntry& entry)
+    auto populateEntry = [&topologyDomainMap,&smtMaskWidth, &coreMaskWidth, &l2CacheMaskShift, &l3CacheMaskShift](TopologyEntry& entry)
     {
         auto getAPICID = [&](const uint32 leaf)
         {
@@ -1218,6 +1217,7 @@ bool PCM::discoverSystemTopology()
         {
             fillEntry(entry, smtMaskWidth, coreMaskWidth, l2CacheMaskShift, getAPICID(0xb));
         }
+        entry.l3_cache_id = extract_bits_32(getAPICID(0xb), l3CacheMaskShift, 31);
     };
 #endif
 
@@ -3231,7 +3231,7 @@ void PCM::printDetailedSystemTopology(const int detailLevel)
         std::cerr << "Tile_Id         ";
         if (detailLevel > 0) std::cerr << "Die_Id          Die_Group_Id    ";
         std::cerr << "Package_Id      Core_Type       Native_CPU_Model\n";
-        std::map<uint32, std::vector<uint32> > os_id_by_core, os_id_by_tile, core_id_by_socket;
+        std::map<uint32, std::vector<uint32> > os_id_by_core, os_id_by_tile, core_id_by_socket, os_id_by_l3_cache;
         size_t counter = 0;
         for (auto it = topology.begin(); it != topology.end(); ++it)
         {
@@ -3252,6 +3252,7 @@ void PCM::printDetailedSystemTopology(const int detailLevel)
             // add socket offset to distinguish cores and tiles from different sockets
             os_id_by_core[(it->socket_id << 15) + it->core_id].push_back(it->os_id);
             os_id_by_tile[(it->socket_id << 15) + it->tile_id].push_back(it->os_id);
+            os_id_by_l3_cache[(it->socket_id << 15) + it->l3_cache_id].push_back(it->os_id);
 
             ++counter;
         }
@@ -3288,6 +3289,16 @@ void PCM::printDetailedSystemTopology(const int detailLevel)
             }
             std::cerr << ")";
         }
+        std::cerr << "\nL3$ ";
+        for (auto core = os_id_by_l3_cache.begin(); core != os_id_by_l3_cache.end(); ++core)
+        {
+            auto os_id = core->second.begin();
+            std::cerr << "(" << *os_id;
+            for (++os_id; os_id != core->second.end(); ++os_id) {
+                std::cerr << "," << *os_id;
+            }
+            std::cerr << ")";
+        }
         std::cerr << "\n";
         std::cerr << "\n";
     }
@@ -7560,14 +7571,23 @@ void PCM::getPCICFGPMUsFromDiscovery(const unsigned int BoxType, const size_t s,
             {
                 std::vector<std::shared_ptr<HWRegister> > CounterControlRegs, CounterValueRegs;
                 const auto n_regs = uncorePMUDiscovery->getBoxNumRegs(BoxType, s, pos);
-                auto makeRegister = [](const uint64 rawAddr)
+                auto makeRegister = [&pos, &numBoxes, &BoxType, &s](const uint64 rawAddr)
                 {
 #ifndef PCI_ENABLE
                     constexpr auto PCI_ENABLE = 0x80000000ULL;
 #endif
                     UncorePMUDiscovery::PCICFGAddress Addr;
                     Addr.raw = rawAddr;
-                    assert(Addr.raw & PCI_ENABLE);
+                    if ((Addr.raw & PCI_ENABLE) == 0)
+                    {
+                        std::cerr << "PCM Error: PCI_ENABLE bit not set in address 0x" << std::hex << Addr.raw << std::dec << "\n";
+                        std::cerr << "This is likely a bug in the uncore PMU discovery BIOS table. Contact your BIOS vendor.\n";
+                        std::cerr << "Socket: " << s << "\n";
+                        std::cerr << "Box type: " << BoxType << "\n";
+                        std::cerr << "Box position: " << pos << "/" << numBoxes << "\n";
+                        std::cerr << "Address: " << Addr.getStr() << "\n";
+                        return std::shared_ptr<PCICFGRegister64>();
+                    }
                     try {
                         auto handle = std::make_shared<PciHandleType>(0, (uint32)Addr.fields.bus,
                                                                         (uint32)Addr.fields.device,

src/lspci.cpp

@@ -94,26 +94,6 @@ bool probe_pci(struct pci *p)
     return p->exist;
 }
 
-void print_pci(struct pci p, const PCIDB & pciDB)
-{
-    printf("Parent bridge info:");
-    printf("%x:%x.%d [%04x:%04x] %s %s %d P:%x S:%x S:%x ",
-            p.bdf.busno, p.bdf.devno, p.bdf.funcno,
-            p.vendor_id, p.device_id,
-            (pciDB.first.count(p.vendor_id) > 0)?pciDB.first.at(p.vendor_id).c_str():"unknown vendor",
-            (pciDB.second.count(p.vendor_id) > 0 && pciDB.second.at(p.vendor_id).count(p.device_id) > 0)?pciDB.second.at(p.vendor_id).at(p.device_id).c_str():"unknown device",
-            p.header_type,
-            p.primary_bus_number, p.secondary_bus_number, p.subordinate_bus_number);
-    printf("Device info:");
-    printf("%x:%x.%d [%04x:%04x] %s %s %d Gen%d x%d\n",
-            p.bdf.busno, p.bdf.devno, p.bdf.funcno,
-            p.vendor_id, p.device_id,
-            (pciDB.first.count(p.vendor_id) > 0)?pciDB.first.at(p.vendor_id).c_str():"unknown vendor",
-            (pciDB.second.count(p.vendor_id) > 0 && pciDB.second.at(p.vendor_id).count(p.device_id) > 0)?pciDB.second.at(p.vendor_id).at(p.device_id).c_str():"unknown device",
-            p.header_type,
-            p.link_speed, p.link_width);
-}
-
 void load_PCIDB(PCIDB & pciDB)
 {
     std::ifstream in(PCI_IDS_PATH);

src/lspci.h

@@ -242,20 +242,6 @@ struct pci {
     bool isIntelDeviceById(uint16_t device_id) const { return (isIntelDevice() && (this->device_id == device_id)); }
 };
 
-struct iio_skx {
-    struct {
-        struct {
-            struct pci root_pci_dev;   /* single device represent root port */
-            std::vector<struct pci> child_pci_devs; /* Contain child switch and end-point devices */
-        } parts[4]{}; /* part 0, 1, 2, 3 */
-        uint8_t busno{}; /* holding busno for each IIO stack */
-        std::string stack_name{};
-        std::vector<uint64_t> values{};
-        bool flipped = false;
-    } stacks[6]; /* iio stack 0, 1, 2, 3, 4, 5 */
-    uint32_t socket_id{};
-};
-
 struct iio_bifurcated_part {
     int part_id{0};
     /* single device represent root port */
@@ -296,8 +282,6 @@ bool probe_pci(struct pci *p);
  */
 typedef std::pair< std::map<int, std::string> ,std::map< int, std::map<int, std::string> > > PCIDB;
 
-void print_pci(struct pci p, const PCIDB & pciDB);
-
 void load_PCIDB(PCIDB & pciDB);
 
 } // namespace pcm

src/pcm-iio-pmu.cpp

@@ -55,7 +55,7 @@ string build_pci_header(const PCIDB & pciDB, uint32_t column_width, const struct
         for (auto& part : p.parts_no) {
             s += std::to_string(part) + ", ";
         }
-        s += "\b\b ";
+        s.erase(s.size() - 2);
     }
 
     /* row with data */