Support for CUTLASS Library generation / Ops / Xe Arch

[Antonyvance]

Intel Xe Architecture Support for CUTLASS Library generation

Feature: Add Intel Xe12/Xe20 architecture support with operation generation and Python bindings.

Use Case: Enable kernel generation for PyTorch inductor path and ML frameworks on Intel Arc/PVC GPUs.

Key Changes:

• Architecture Support: Added Xe12 (PVC) and Xe20 (BMG) with compute capability 12-50
• Operations: FP16, BF16, FP8 (E4M3/E5M2), INT8 GEMM kernels with multiple tile sizes (256×256, 128×256, etc.)
• Build Flags: New CMake options -DCUTLASS_LIBRARY_GENERATOR_ARCHS="20" for Intel GPU targets
• Python Integration: CMake-based shared library (examples/11_xe20_cutlass_library/) + ctypes bindings
• Generator: Extended python/cutlass_library/generator.py with GenerateIntelXe() functions
• Examples: Python test scripts with performance benchmarking

Testing: ✅ Tested BF16 generated kernels, Examples, Documentation

Note These changes do not make use of new APIs (or modified collectives). That must be different feature / refactoring effort.

ToDo:

• Build Failures
• Benchmark tests for comprehensive performance analysis
• Testing kernels beyond BF16 (FP16, FP8, INT8)
• Optimizing generated kernels with tile sizes
• Modify CMake to avoid explicitly linking with libsycl.so

Type: Feature | Tested On: Xe20 ✅