External Release v2025.03.02

The release updates XED according to Intel's latest ISA publications, including
AVX10.2 (Revision 3.0) and APX (Revision 6.0) architecture specifications.
This release also introduces major enhancements to the decoder control APIs.

ISA Updates
- Added new APX instructions that promote the Diamond Rapids ISA.
- Added support for AVX10.2 mnemonic renames.
- Improved definitions for Intel SDM-recommended multi-byte NOPs (See
  #340).
- Fixed ISA-SET discrepancy for FISTTP.
- Corrected element types for VCVTQQ2PD and VGET{MANT,EXP}PBF16 instructions.
- Refined TSX ISA definition for accurate disassembly representation.
- Dropped compatibility mode SYSCALL per Intel's latest FRED specification.
- Added missing `PROTECTED_MODE` and `NOP` XED attributes for existing ISA.

-----
General
- Python APIs: The `_py` binding APIs are now autogenerated during the build for
  an accurate representation of the chosen build kit. For more information, check
  the `xed\pyext\examples\README.md` file.
- Python APIs example: Enhancements for the CFFI example and XedPy class.
- Updated the XED build to support Clang versions 17 and 18.
- Improved XED examples documentation and source-code comments.
- Simplified the encode request for AVX10/256VL Embedded Rounding Control
  instructions by setting only the `ROUNDC` XED operand.

-----
Fixes
- Fixed UBSan errors (closes #339).
- Fixed Sierra-Forest and other chip-excluded builds using the `--no-{chip}` build 
  knobs (fixes #343).
- Corrected SIB segment mapping for the R21 register (fixes #340).
- Internal improvements and code cleanup (fixes #340).

-----
Decoder
- Added REAL-mode legality checks (`INVALID_MODE` error for illegal instructions).
- Disassembler: Added support for Intel's recommended APX assembly syntax for NF
  (No Flags) and DFV (Default Flags Values) instructions.
- Enhanced APIs for APX/DFV instructions to ensure simplicity and efficiency. See
  the API reference page and the `xed-ex1.c` example for more details.

-----
API Improvements for Decoder ISA Control

The XED decoder control APIs now fully support the `xed_chip_features_t`
structure, offering greater flexibility and control compared to the
`xed_chip_enum_t` concept, enabling users to customize feature sets with
precision.
- Improved the `xed_chip_features_t` APIs to provide fine-grained control over
  ISA initialization. This approach is now recommended over the raw
  `xed3_operand_set_*` APIs.
- Introduced a new API, `xed_set_decoder_modes()`, which allows explicit
  initialization of decoder modes with improved performance through one-time
  decoder ISA initialization.

Backward Compatibility
- Backward compatibility for existing APIs is maintained.
- Backward compatibility for decoder initialization of several ISA features has
  been deprecated. Previously default-on features like `P4` (PAUSE), `LZCNT`
  (replacing BSR), and `TZCNT` (replacing BSF) are now disabled by default unless
  explicitly enabled by users through the raw XED setter APIs or the
  chip/chip-features APIs.

Decoder PREFETCH as NOP - New Capability
- Based on decoder ISA initialization, the XED decoder now returns NOPs instead
  of PREFETCH instructions when PREFETCH is not supported by the chip/features.
  Previously, PREFETCH instructions were returned as illegal if they were 
  unsupported by the XED chip

Usage Example
- For detailed usage guidance, refer to the XED `xed-ex4.c` example tool, which
  includes decoder initialization recommendations for dual-encoding ISA.


Co-authored-by: marjevan <marjevan@users.noreply.github.com>

Author: sdeadmin

VERSION

@@ -1 +1 @@
-v2024.11.04
+v2025.03.02

datafiles/amd/xed-amd-base.txt

@@ -1,6 +1,6 @@
 #BEGIN_LEGAL
 #
-#Copyright (c) 2023 Intel Corporation
+#Copyright (c) 2024 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -18,10 +18,10 @@
 # file: xed-amd-base.txt
 
 INSTRUCTIONS()::
-# SYSRET is supported in 32b mode only on AMD chips
+# SYSCALL and SYSRET are supported in 32b mode only on AMD chips
+
 {
 ICLASS    : SYSCALL_AMD
-UNAME     : AMDSYSCALL32
 DISASM    : syscall
 CPL       : 3
 CATEGORY  : SYSCALL

datafiles/amx-dmr/amx-dmr-isa.xed.txt

@@ -57,9 +57,9 @@ IFORM:       TCVTROWD2PS_ZMMf32_TMMu32_IMM8
 }
 
 
-# EMITTING TCVTROWPS2PBF16H (TCVTROWPS2PBF16H-512-1)
+# EMITTING TCVTROWPS2BF16H (TCVTROWPS2BF16H-512-1)
 {
-ICLASS:      TCVTROWPS2PBF16H
+ICLASS:      TCVTROWPS2BF16H
 CPL:         3
 CATEGORY:    AMX_TILE
 EXTENSION:   AMX_TILE
@@ -69,13 +69,13 @@ REAL_OPCODE: Y
 ATTRIBUTES:  NOTSX 
 PATTERN:     EVV 0x6D VF2 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 ZEROING=0 MASK=0
 OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=TMM_B3():r:tv:f32 REG2=GPR32_N():r:d:u32
-IFORM:       TCVTROWPS2PBF16H_ZMMbf16_TMMf32_GPR32u32
+IFORM:       TCVTROWPS2BF16H_ZMMbf16_TMMf32_GPR32u32
 }
 
 
-# EMITTING TCVTROWPS2PBF16H (TCVTROWPS2PBF16H-512-2)
+# EMITTING TCVTROWPS2BF16H (TCVTROWPS2BF16H-512-2)
 {
-ICLASS:      TCVTROWPS2PBF16H
+ICLASS:      TCVTROWPS2BF16H
 CPL:         3
 CATEGORY:    AMX_TILE
 EXTENSION:   AMX_TILE
@@ -85,13 +85,13 @@ REAL_OPCODE: Y
 ATTRIBUTES:  NOTSX 
 PATTERN:     EVV 0x07 VF2 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=TMM_B3():r:tv:f32 IMM0:r:b
-IFORM:       TCVTROWPS2PBF16H_ZMMbf16_TMMf32_IMM8
+IFORM:       TCVTROWPS2BF16H_ZMMbf16_TMMf32_IMM8
 }
 
 
-# EMITTING TCVTROWPS2PBF16L (TCVTROWPS2PBF16L-512-1)
+# EMITTING TCVTROWPS2BF16L (TCVTROWPS2BF16L-512-1)
 {
-ICLASS:      TCVTROWPS2PBF16L
+ICLASS:      TCVTROWPS2BF16L
 CPL:         3
 CATEGORY:    AMX_TILE
 EXTENSION:   AMX_TILE
@@ -101,13 +101,13 @@ REAL_OPCODE: Y
 ATTRIBUTES:  NOTSX 
 PATTERN:     EVV 0x6D VF3 V0F38 MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 ZEROING=0 MASK=0
 OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=TMM_B3():r:tv:f32 REG2=GPR32_N():r:d:u32
-IFORM:       TCVTROWPS2PBF16L_ZMMbf16_TMMf32_GPR32u32
+IFORM:       TCVTROWPS2BF16L_ZMMbf16_TMMf32_GPR32u32
 }
 
 
-# EMITTING TCVTROWPS2PBF16L (TCVTROWPS2PBF16L-512-2)
+# EMITTING TCVTROWPS2BF16L (TCVTROWPS2BF16L-512-2)
 {
-ICLASS:      TCVTROWPS2PBF16L
+ICLASS:      TCVTROWPS2BF16L
 CPL:         3
 CATEGORY:    AMX_TILE
 EXTENSION:   AMX_TILE
@@ -117,7 +117,7 @@ REAL_OPCODE: Y
 ATTRIBUTES:  NOTSX 
 PATTERN:     EVV 0x77 VF3 V0F3A MOD[0b11] MOD=3 BCRC=0 UBIT=1 REG[rrr] RM[nnn] W0 VL512 mode64 NOEVSR ZEROING=0 MASK=0 UIMM8()
 OPERANDS:    REG0=ZMM_R3():w:zbf16 REG1=TMM_B3():r:tv:f32 IMM0:r:b
-IFORM:       TCVTROWPS2PBF16L_ZMMbf16_TMMf32_IMM8
+IFORM:       TCVTROWPS2BF16L_ZMMbf16_TMMf32_IMM8
 }
 
 

datafiles/apx-f/README.md

@@ -21,9 +21,8 @@ Encode request for promoted No-Flags instruction should be built with the `NF` o
     $ xed.exe -set NF 1 ....
     ```
 
-## CCMPcc/CTESTcc (Encode/Decode)
-The official Intel® APX assembly syntax is not supported yet. 
-Current syntax is: `<MNEMONIC> <reg/mem>, <reg/mem/imm>, <dfv>`
+## CCMPcc/CTESTcc (XED CLI Encoder)
+Intel&reg; XED CLI encode request syntax: `xed -64 -set DFV <int> -e <MNEMONIC> <reg/mem>, <reg/mem/imm>`
 
 ## IMUL/SETcc Zero-Upper variants (Encoder)
 No encoder support for zero-upper selection

datafiles/apx-f/apx-evex-dec.txt

@@ -1,6 +1,6 @@
 #BEGIN_LEGAL
 #
-#Copyright (c) 2023 Intel Corporation
+#Copyright (c) 2025 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -43,6 +43,28 @@ EVAPX()::
     NO_APX=0 NF=1 MASK=4 | EVEX_APX  MASK=0 SCC=0 BCRC=0
     # Default: otherwise | error 
 
+DFV_PARSER()::
+    # The DFV xed-operand is an integer representation for default flags values - (OF, SF, ZF, CF). 
+    # For example: DFV=10 == 0b1010  ->  OF=1, SF=0, ZF=1, CF=0
+    VEXDEST3=0 VEXDEST210=0 | DFV=0
+    VEXDEST3=0 VEXDEST210=1 | DFV=1
+    VEXDEST3=0 VEXDEST210=2 | DFV=2
+    VEXDEST3=0 VEXDEST210=3 | DFV=3
+    VEXDEST3=0 VEXDEST210=4 | DFV=4
+    VEXDEST3=0 VEXDEST210=5 | DFV=5
+    VEXDEST3=0 VEXDEST210=6 | DFV=6
+    VEXDEST3=0 VEXDEST210=7 | DFV=7
+    
+    VEXDEST3=1 VEXDEST210=0 | DFV=8
+    VEXDEST3=1 VEXDEST210=1 | DFV=9
+    VEXDEST3=1 VEXDEST210=2 | DFV=10
+    VEXDEST3=1 VEXDEST210=3 | DFV=11
+    VEXDEST3=1 VEXDEST210=4 | DFV=12
+    VEXDEST3=1 VEXDEST210=5 | DFV=13
+    VEXDEST3=1 VEXDEST210=6 | DFV=14
+    VEXDEST3=1 VEXDEST210=7 | DFV=15
+
 EVAPX_SCC()::
-    # Clear Legacy reinterpreted bits by the SCC field and set EVEX sub-encoding space
-    true  | EVEX_APX_SCC MASK=0 VEXDEST4=0 NF=0 BCRC=0
+    # - Clear Legacy reinterpreted bits by the SCC field and set EVEX sub-encoding space
+    # - Set the DFV operand value
+    true DFV_PARSER() | EVEX_APX_SCC MASK=0 VEXDEST4=0 NF=0 BCRC=0

datafiles/apx-f/apx-evex-enc.txt

@@ -1,6 +1,6 @@
 #BEGIN_LEGAL
 #
-#Copyright (c) 2023 Intel Corporation
+#Copyright (c) 2025 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -97,23 +97,22 @@ EVAPX()::
     true      -> EVEX_APX
 
 EVAPX_SCC()::
-    # SSC reinterprets the original EVEX encoding bits (VEXDEST4(V4) and MASK(aaaa)).
-    # Note the ILD store the inverted VEXDEST4 value, just like the encoded bit.
-    #                     -> SCC     EVEX encoding sub-space  Clear original interpretation
-    VEXDEST4=1  MASK=0    ->  SCC=0        EVEX_APX_SCC                VEXDEST4=0
-    VEXDEST4=1  MASK=1    ->  SCC=1        EVEX_APX_SCC         MASK=0 VEXDEST4=0
-    VEXDEST4=1  MASK=2    ->  SCC=2        EVEX_APX_SCC         MASK=0 VEXDEST4=0
-    VEXDEST4=1  MASK=3    ->  SCC=3        EVEX_APX_SCC         MASK=0 VEXDEST4=0
-    VEXDEST4=1  MASK=4    ->  SCC=4        EVEX_APX_SCC         MASK=0 VEXDEST4=0
-    VEXDEST4=1  MASK=5    ->  SCC=5        EVEX_APX_SCC         MASK=0 VEXDEST4=0
-    VEXDEST4=1  MASK=6    ->  SCC=6        EVEX_APX_SCC         MASK=0 VEXDEST4=0
-    VEXDEST4=1  MASK=7    ->  SCC=7        EVEX_APX_SCC         MASK=0 VEXDEST4=0
-    VEXDEST4=0  MASK=0    ->  SCC=8        EVEX_APX_SCC
-    VEXDEST4=0  MASK=1    ->  SCC=9        EVEX_APX_SCC         MASK=0
-    VEXDEST4=0  MASK=2    ->  SCC=10       EVEX_APX_SCC         MASK=0
-    VEXDEST4=0  MASK=3    ->  SCC=11       EVEX_APX_SCC         MASK=0
-    VEXDEST4=0  MASK=4    ->  SCC=12       EVEX_APX_SCC         MASK=0
-    VEXDEST4=0  MASK=5    ->  SCC=13       EVEX_APX_SCC         MASK=0
-    VEXDEST4=0  MASK=6    ->  SCC=14       EVEX_APX_SCC         MASK=0
-    VEXDEST4=0  MASK=7    ->  SCC=15       EVEX_APX_SCC         MASK=0
+# The APX DFV (Defaults Flags Values) data is encoded in EVEX.vvvv
+    DFV=0  -> VEXDEST3=0 VEXDEST210=0 EVEX_APX_SCC
+    DFV=1  -> VEXDEST3=0 VEXDEST210=1 EVEX_APX_SCC
+    DFV=2  -> VEXDEST3=0 VEXDEST210=2 EVEX_APX_SCC
+    DFV=3  -> VEXDEST3=0 VEXDEST210=3 EVEX_APX_SCC
+    DFV=4  -> VEXDEST3=0 VEXDEST210=4 EVEX_APX_SCC
+    DFV=5  -> VEXDEST3=0 VEXDEST210=5 EVEX_APX_SCC
+    DFV=6  -> VEXDEST3=0 VEXDEST210=6 EVEX_APX_SCC
+    DFV=7  -> VEXDEST3=0 VEXDEST210=7 EVEX_APX_SCC
+    DFV=8  -> VEXDEST3=1 VEXDEST210=0 EVEX_APX_SCC
+    DFV=9  -> VEXDEST3=1 VEXDEST210=1 EVEX_APX_SCC
+    DFV=10 -> VEXDEST3=1 VEXDEST210=2 EVEX_APX_SCC
+    DFV=11 -> VEXDEST3=1 VEXDEST210=3 EVEX_APX_SCC
+    DFV=12 -> VEXDEST3=1 VEXDEST210=4 EVEX_APX_SCC
+    DFV=13 -> VEXDEST3=1 VEXDEST210=5 EVEX_APX_SCC
+    DFV=14 -> VEXDEST3=1 VEXDEST210=6 EVEX_APX_SCC
+    DFV=15 -> VEXDEST3=1 VEXDEST210=7 EVEX_APX_SCC
+
 ######################################################

datafiles/apx-f/apx-evgpr-reg-tables.txt

@@ -1,6 +1,6 @@
 #BEGIN_LEGAL
 #
-#Copyright (c) 2023 Intel Corporation
+#Copyright (c) 2025 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -247,29 +247,3 @@ REXB4=1 REXB=1 RM=0x5  | OUTREG=XED_REG_R29 HAS_EGPR=1
 REXB4=1 REXB=1 RM=0x6  | OUTREG=XED_REG_R30 HAS_EGPR=1
 REXB4=1 REXB=1 RM=0x7  | OUTREG=XED_REG_R31 HAS_EGPR=1
 
-
-
-########################################################
-
-xed_reg_enum_t DFV()::
-# Enumeration for EVEX.[OF, SF, ZF, CF] default flags.
-# The register index represents the default flags values. For example:
-# DFV10.index == 10 == 0b1010  ->  OF=1, SF=0, ZF=1, CF=0
-VEXDEST3=0 VEXDEST210=0 | OUTREG=XED_REG_DFV0
-VEXDEST3=0 VEXDEST210=1 | OUTREG=XED_REG_DFV1
-VEXDEST3=0 VEXDEST210=2 | OUTREG=XED_REG_DFV2
-VEXDEST3=0 VEXDEST210=3 | OUTREG=XED_REG_DFV3
-VEXDEST3=0 VEXDEST210=4 | OUTREG=XED_REG_DFV4
-VEXDEST3=0 VEXDEST210=5 | OUTREG=XED_REG_DFV5
-VEXDEST3=0 VEXDEST210=6 | OUTREG=XED_REG_DFV6
-VEXDEST3=0 VEXDEST210=7 | OUTREG=XED_REG_DFV7
-
-VEXDEST3=1 VEXDEST210=0 | OUTREG=XED_REG_DFV8
-VEXDEST3=1 VEXDEST210=1 | OUTREG=XED_REG_DFV9
-VEXDEST3=1 VEXDEST210=2 | OUTREG=XED_REG_DFV10
-VEXDEST3=1 VEXDEST210=3 | OUTREG=XED_REG_DFV11
-VEXDEST3=1 VEXDEST210=4 | OUTREG=XED_REG_DFV12
-VEXDEST3=1 VEXDEST210=5 | OUTREG=XED_REG_DFV13
-VEXDEST3=1 VEXDEST210=6 | OUTREG=XED_REG_DFV14
-VEXDEST3=1 VEXDEST210=7 | OUTREG=XED_REG_DFV15
-