External Release v2025.11.23

This release aligns XED with the latest Intel architecture specifications,
including:
- Intel SDM Revision 089
- Intel ISE Revision 059
- Intel APX Revision 7.0

---

Key ISA updates:
- Dropped support for AMX-TRANSPOSE instructions.
- Updated CPUID sensitivity for several APX instructions to include the
  APX_NCI_NDD_NF bit.
- Added support for the UDB undefined instruction.
- Updated the supported chip list for the PBNDKB instruction.

---

General improvements:
- Refactored XED extensions for APX-promoted instructions to align with
  legacy ISA extensions. This treats APX promotions as ISA optimizations
  rather than new extensions, improving XED classification.
- Added a new XED classifier for APX-F (Foundation) instructions. 
  Note: The existing xed_classify_apx() API is unchanged and continues 
  to detect instructions with APX-specific encodings.
- Renamed the RAO_INT XED extension to RAO.
- Enhanced the XED builder to include XedPy Python sources and examples
  when the --xedpy build knob is used.
- Improved pysrc/gen_cpuid.py output by supporting grouped CPUID information
  and filtering duplicate entries.
- Added extended documentation and a new README file for XED pysrc scripts.
- Improved builder error messaging by removing the "fatal" token from
  non-verbose builds that encounter a failed git describe, preventing
  confusion during build failures.
- Renamed the AMD/VIA-enabled build option to AMD/VIA.

---

Fixes:
- Added missing RING0 attributes for multiple instructions 
  (Fixes #350).
- Dropped CLDEMOTE from ADL.
- Fixed the examples/mfile.py builder to support manual, direct execution
  inside the XED kit.
- Added missing XED APIs in the dynamic XED build (Fixes #353).
- Fixed XED examples Clang 19 build warnings (Fixes #354, 
  closes #351).
- Improved ENC2 resilience with multiple internal stability enhancements
  (Fixes #355).
- Marked xed_decoded_inst_get_byte() as a private API, as it is not intended
  or safe for library consumers.
- Dropped a redundant XED_DLL_GLOBAL library C macro (Fixes #352).
- Fixed the XED library build when MPX support is excluded.


Co-authored-by: marjevan <marjevan@users.noreply.github.com>

Author: sdeadmin

VERSION

@@ -1 +1 @@
-v2025.06.08
+v2025.11.23

datafiles/adl/adl-chips.txt

@@ -1,6 +1,6 @@
 #BEGIN_LEGAL
 #
-#Copyright (c) 2022 Intel Corporation
+#Copyright (c) 2025 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -22,6 +22,7 @@ ALDER_LAKE:             \
      ALL_OF(SNOW_RIDGE) \
      NOT(SGX_ENCLV)     \
      NOT(MPX)           \
+     NOT(CLDEMOTE)      \
      KEYLOCKER          \
      KEYLOCKER_WIDE     \
      CET                \
@@ -44,8 +45,7 @@ ALDER_LAKE:             \
      ADOX_ADCX          \
      LZCNT              \
      WBNOINVD           \
-     HRESET             \
-     CLDEMOTE
+     HRESET             
 
 
 

datafiles/amd/xed-amd-invlpgb.txt

@@ -22,7 +22,7 @@ ICLASS    : INVLPGB
 CPL       : 0
 CATEGORY  : SYSTEM
 EXTENSION : AMD_INVLPGB
-ATTRIBUTES: AMDONLY
+ATTRIBUTES: RING0 AMDONLY
 COMMENT   : Is this 64b mode only?
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] no_refining_prefix eamode32
 OPERANDS  : REG0=XED_REG_EAX:r:SUPP \
@@ -38,7 +38,7 @@ ICLASS    : TLBSYNC
 CPL       : 0
 CATEGORY  : SYSTEM
 EXTENSION : AMD_INVLPGB
-ATTRIBUTES: AMDONLY
+ATTRIBUTES: RING0 AMDONLY
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] no_refining_prefix
 OPERANDS  : 
 }

datafiles/amd/xed-amd-snp.txt

@@ -1,6 +1,6 @@
 #BEGIN_LEGAL
 #
-#Copyright (c) 2020 Intel Corporation
+#Copyright (c) 2025 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -22,7 +22,7 @@ ICLASS    : PSMASH
 CPL       : 0
 CATEGORY  : SYSTEM
 EXTENSION : SNP
-ATTRIBUTES: AMDONLY
+ATTRIBUTES: RING0 AMDONLY
 FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod ]
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f3_refining_prefix mode64
 OPERANDS  : REG0=XED_REG_RAX:rw:IMPL
@@ -34,7 +34,7 @@ ICLASS    : PVALIDATE
 CPL       : 0
 CATEGORY  : SYSTEM
 EXTENSION : SNP
-ATTRIBUTES: AMDONLY
+ATTRIBUTES: RING0 AMDONLY
 FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod cf-mod ]
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b111] f2_refining_prefix
 OPERANDS  : REG0=XED_REG_RAX:rw:IMPL REG1=XED_REG_ECX:r:IMPL REG2=XED_REG_EDX:r:IMPL
@@ -46,7 +46,7 @@ ICLASS    : RMPADJUST
 CPL       : 0
 CATEGORY  : SYSTEM
 EXTENSION : SNP
-ATTRIBUTES: AMDONLY
+ATTRIBUTES: RING0 AMDONLY
 FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod  ]
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f3_refining_prefix mode64
 OPERANDS  : REG0=XED_REG_RAX:rw:IMPL REG1=XED_REG_RCX:r:IMPL REG2=XED_REG_RDX:r:IMPL
@@ -57,7 +57,7 @@ ICLASS    : RMPUPDATE
 CPL       : 0
 CATEGORY  : SYSTEM
 EXTENSION : SNP
-ATTRIBUTES: AMDONLY
+ATTRIBUTES: RING0 AMDONLY
 FLAGS     : MUST [ of-mod sf-mod zf-mod af-mod pf-mod  ]
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] f2_refining_prefix mode64
 OPERANDS  : REG0=XED_REG_RAX:rw:IMPL REG1=XED_REG_RCX:r:IMPL 

datafiles/amd/xed-amd-svm.txt

@@ -1,6 +1,6 @@
 #BEGIN_LEGAL
 #
-#Copyright (c) 2020 Intel Corporation
+#Copyright (c) 2025 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -84,7 +84,7 @@ ICLASS    : INVLPGA
 CPL       : 0
 CATEGORY  : SYSTEM
 EXTENSION : SVM
-ATTRIBUTES: PROTECTED_MODE AMDONLY
+ATTRIBUTES: RING0 PROTECTED_MODE AMDONLY
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b011] RM[0b111] 
 OPERANDS  : REG0=ArAX():r:IMPL REG1=XED_REG_ECX:r:IMPL
 }

datafiles/amx-dmr/amx-dmr-isa.xed.txt

@@ -218,166 +218,6 @@ IFORM:       TILEMOVROW_ZMMu8_TMMu8_GPR32u32
 
 
 AVX_INSTRUCTIONS()::
-# EMITTING T2RPNTLVWZ0 (T2RPNTLVWZ0-128-1)
-{
-ICLASS:      T2RPNTLVWZ0
-CPL:         3
-CATEGORY:    AMX_TILE
-EXTENSION:   AMX_TILE
-ISA_SET:     AMX_TRANSPOSE
-EXCEPTIONS:  AMX-E11
-REAL_OPCODE: Y
-ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0x6E VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
-OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
-IFORM:       T2RPNTLVWZ0_TMM2u16_MEMu16
-}
-
-
-# EMITTING T2RPNTLVWZ0RS (T2RPNTLVWZ0RS-128-1)
-{
-ICLASS:      T2RPNTLVWZ0RS
-CPL:         3
-CATEGORY:    AMX_TILE
-EXTENSION:   AMX_TILE
-ISA_SET:     AMX_TRANSPOSE_MOVRS
-EXCEPTIONS:  AMX-E11
-REAL_OPCODE: Y
-ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0xF8 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
-OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
-IFORM:       T2RPNTLVWZ0RS_TMM2u16_MEMu16
-}
-
-
-# EMITTING T2RPNTLVWZ0RST1 (T2RPNTLVWZ0RST1-128-1)
-{
-ICLASS:      T2RPNTLVWZ0RST1
-CPL:         3
-CATEGORY:    AMX_TILE
-EXTENSION:   AMX_TILE
-ISA_SET:     AMX_TRANSPOSE_MOVRS
-EXCEPTIONS:  AMX-E11
-REAL_OPCODE: Y
-ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0xF9 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
-OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
-IFORM:       T2RPNTLVWZ0RST1_TMM2u16_MEMu16
-}
-
-
-# EMITTING T2RPNTLVWZ0T1 (T2RPNTLVWZ0T1-128-1)
-{
-ICLASS:      T2RPNTLVWZ0T1
-CPL:         3
-CATEGORY:    AMX_TILE
-EXTENSION:   AMX_TILE
-ISA_SET:     AMX_TRANSPOSE
-EXCEPTIONS:  AMX-E11
-REAL_OPCODE: Y
-ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0x6F VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
-OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
-IFORM:       T2RPNTLVWZ0T1_TMM2u16_MEMu16
-}
-
-
-# EMITTING T2RPNTLVWZ1 (T2RPNTLVWZ1-128-1)
-{
-ICLASS:      T2RPNTLVWZ1
-CPL:         3
-CATEGORY:    AMX_TILE
-EXTENSION:   AMX_TILE
-ISA_SET:     AMX_TRANSPOSE
-EXCEPTIONS:  AMX-E11
-REAL_OPCODE: Y
-ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0x6E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
-OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
-IFORM:       T2RPNTLVWZ1_TMM2u16_MEMu16
-}
-
-
-# EMITTING T2RPNTLVWZ1RS (T2RPNTLVWZ1RS-128-1)
-{
-ICLASS:      T2RPNTLVWZ1RS
-CPL:         3
-CATEGORY:    AMX_TILE
-EXTENSION:   AMX_TILE
-ISA_SET:     AMX_TRANSPOSE_MOVRS
-EXCEPTIONS:  AMX-E11
-REAL_OPCODE: Y
-ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0xF8 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
-OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
-IFORM:       T2RPNTLVWZ1RS_TMM2u16_MEMu16
-}
-
-
-# EMITTING T2RPNTLVWZ1RST1 (T2RPNTLVWZ1RST1-128-1)
-{
-ICLASS:      T2RPNTLVWZ1RST1
-CPL:         3
-CATEGORY:    AMX_TILE
-EXTENSION:   AMX_TILE
-ISA_SET:     AMX_TRANSPOSE_MOVRS
-EXCEPTIONS:  AMX-E11
-REAL_OPCODE: Y
-ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0xF9 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
-OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
-IFORM:       T2RPNTLVWZ1RST1_TMM2u16_MEMu16
-}
-
-
-# EMITTING T2RPNTLVWZ1T1 (T2RPNTLVWZ1T1-128-1)
-{
-ICLASS:      T2RPNTLVWZ1T1
-CPL:         3
-CATEGORY:    AMX_TILE
-EXTENSION:   AMX_TILE
-ISA_SET:     AMX_TRANSPOSE
-EXCEPTIONS:  AMX-E11
-REAL_OPCODE: Y
-ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0x6F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
-OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
-IFORM:       T2RPNTLVWZ1T1_TMM2u16_MEMu16
-}
-
-
-# EMITTING TCONJTCMMIMFP16PS (TCONJTCMMIMFP16PS-128-1)
-{
-ICLASS:      TCONJTCMMIMFP16PS
-CPL:         3
-CATEGORY:    AMX_TILE
-EXTENSION:   AMX_TILE
-ISA_SET:     AMX_TRANSPOSE_COMPLEX
-EXCEPTIONS:  AMX-E10
-REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX NO_REG_MATCH 
-PATTERN:     VV1 0x6B VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
-OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:2f16 REG2=TMM_N():r:tv:2f16
-IFORM:       TCONJTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16
-}
-
-
-# EMITTING TCONJTFP16 (TCONJTFP16-128-1)
-{
-ICLASS:      TCONJTFP16
-CPL:         3
-CATEGORY:    AMX_TILE
-EXTENSION:   AMX_TILE
-ISA_SET:     AMX_TRANSPOSE_COMPLEX
-EXCEPTIONS:  AMX-E9
-REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX 
-PATTERN:     VV1 0x6B V66 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64 NOVSR
-OPERANDS:    REG0=TMM_R():w:tv:2f16 REG1=TMM_B():r:tv:2f16
-IFORM:       TCONJTFP16_TMM2f16_TMM2f16
-}
-
-
 # EMITTING TDPBF8PS (TDPBF8PS-128-1)
 {
 ICLASS:      TDPBF8PS
@@ -490,99 +330,3 @@ IFORM:       TMMULTF32PS_TMMf32_TMMf32_TMMf32
 }
 
 
-# EMITTING TTCMMIMFP16PS (TTCMMIMFP16PS-128-1)
-{
-ICLASS:      TTCMMIMFP16PS
-CPL:         3
-CATEGORY:    AMX_TILE
-EXTENSION:   AMX_TILE
-ISA_SET:     AMX_TRANSPOSE_COMPLEX
-EXCEPTIONS:  AMX-E10
-REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX NO_REG_MATCH 
-PATTERN:     VV1 0x6B VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
-OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:2f16 REG2=TMM_N():r:tv:2f16
-IFORM:       TTCMMIMFP16PS_TMMf32_TMM2f16_TMM2f16
-}
-
-
-# EMITTING TTCMMRLFP16PS (TTCMMRLFP16PS-128-1)
-{
-ICLASS:      TTCMMRLFP16PS
-CPL:         3
-CATEGORY:    AMX_TILE
-EXTENSION:   AMX_TILE
-ISA_SET:     AMX_TRANSPOSE_COMPLEX
-EXCEPTIONS:  AMX-E10
-REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX NO_REG_MATCH 
-PATTERN:     VV1 0x6B VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
-OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:2f16 REG2=TMM_N():r:tv:2f16
-IFORM:       TTCMMRLFP16PS_TMMf32_TMM2f16_TMM2f16
-}
-
-
-# EMITTING TTDPBF16PS (TTDPBF16PS-128-1)
-{
-ICLASS:      TTDPBF16PS
-CPL:         3
-CATEGORY:    AMX_TILE
-EXTENSION:   AMX_TILE
-ISA_SET:     AMX_TRANSPOSE_BF16
-EXCEPTIONS:  AMX-E10
-REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX NO_REG_MATCH 
-PATTERN:     VV1 0x6C VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
-OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:bf16 REG2=TMM_N():r:tv:bf16
-IFORM:       TTDPBF16PS_TMMf32_TMMbf16_TMMbf16
-}
-
-
-# EMITTING TTDPFP16PS (TTDPFP16PS-128-1)
-{
-ICLASS:      TTDPFP16PS
-CPL:         3
-CATEGORY:    AMX_TILE
-EXTENSION:   AMX_TILE
-ISA_SET:     AMX_TRANSPOSE_FP16
-EXCEPTIONS:  AMX-E10
-REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX NO_REG_MATCH 
-PATTERN:     VV1 0x6C VF2 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
-OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:f16 REG2=TMM_N():r:tv:f16
-IFORM:       TTDPFP16PS_TMMf32_TMMf16_TMMf16
-}
-
-
-# EMITTING TTMMULTF32PS (TTMMULTF32PS-128-1)
-{
-ICLASS:      TTMMULTF32PS
-CPL:         3
-CATEGORY:    AMX_TILE
-EXTENSION:   AMX_TILE
-ISA_SET:     AMX_TRANSPOSE_TF32
-EXCEPTIONS:  AMX-E10
-REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX NO_REG_MATCH 
-PATTERN:     VV1 0x48 VNP V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64
-OPERANDS:    REG0=TMM_R():rw:tv:f32 REG1=TMM_B():r:tv:f32 REG2=TMM_N():r:tv:f32
-IFORM:       TTMMULTF32PS_TMMf32_TMMf32_TMMf32
-}
-
-
-# EMITTING TTRANSPOSED (TTRANSPOSED-128-1)
-{
-ICLASS:      TTRANSPOSED
-CPL:         3
-CATEGORY:    AMX_TILE
-EXTENSION:   AMX_TILE
-ISA_SET:     AMX_TRANSPOSE
-EXCEPTIONS:  AMX-E9
-REAL_OPCODE: Y
-ATTRIBUTES:  NOTSX 
-PATTERN:     VV1 0x5F VF3 V0F38 MOD[0b11] MOD=3 REG[rrr] RM[nnn] W0 VL128 mode64 NOVSR
-OPERANDS:    REG0=TMM_R():w:tv:u32 REG1=TMM_B():r:tv:u32
-IFORM:       TTRANSPOSED_TMMu32_TMMu32
-}
-
-

datafiles/amx-dmr/cpuid.xed.txt

@@ -17,17 +17,10 @@
 #END_LEGAL
 
 XED_ISA_SET_AMX_FP8             : amx_fp8.1e.1.eax.4
-XED_ISA_SET_AMX_TRANSPOSE       : amx_transpose.1e.1.eax.5
 XED_ISA_SET_AMX_TF32            : amx_tf32.1e.1.eax.6
 XED_ISA_SET_AMX_AVX512          : amx_avx512.1e.1.eax.7
 XED_ISA_SET_AMX_MOVRS           : amx_movrs.1e.1.eax.8
 
-XED_ISA_SET_AMX_TRANSPOSE_MOVRS : amx_transpose.1e.1.eax.5 amx_movrs.1e.1.eax.8
-XED_ISA_SET_AMX_TRANSPOSE_COMPLEX : amx_transpose.1e.1.eax.5 amx_complex_mirrored.1e.1.eax.2
-XED_ISA_SET_AMX_TRANSPOSE_BF16 : amx_transpose.1e.1.eax.5 amx_bf16_mirrored.1e.1.eax.1
-XED_ISA_SET_AMX_TRANSPOSE_FP16 : amx_transpose.1e.1.eax.5 amx_fp16_mirrored.1e.1.eax.3
-XED_ISA_SET_AMX_TRANSPOSE_TF32 : amx_transpose.1e.1.eax.5 amx_tf32.1e.1.eax.6
-
 # Starting with AVX10, feature bits for state-features have moved to their own leaf. 
 # This change provides a single location for developers to find feature bits, simplifying 
 # the process.