External Release v2025.06.08

This release aligns XED with Intel’s latest architecture specifications, including:
- Intel® SDM Revision 087
- Intel® ISE Revision 057
- Intel® AVX10.2 Revision 5.0

Key ISA-related changes:
- Dropped support for AVX10/256-specific architectural features, including YMM embedded rounding and AVX10 VL-specific CPUID enumerations
- Updated CPUID sensitivity for various AVX10.2 instructions
- Updated exception class handling for several AVX512 instructions

---

### General

- Modified arguments of the `xed_operand_print()` decoder API to correctly represent the destination EVEX operand (the old signature is deprecated and replaced)
- Restructured XED examples for improved clarity, naming, and usability
- Improved XedPy with more robust initialization and initial high-level Python encode APIs
- Migrated internal types to use `stdint.h` exclusively
- Added ENC2 support for REX2 prefix encoding with EGPR operands

---

### Fixes

- Fixed many build exclusion options; deprecated several build flavors in favor of `--no-avx512` as the minimal build kit (Fixes #336)
- Encoder: fixed AMX encoding for non-index SIBMEM operands
- Added missing and removed incorrect non-temporal memory hints
- Resolved Python 3.12 compatibility warnings (Closes #346)
- Fixed AMD `INVLPGB` operand specification (Closes #345)
- Corrected AMD `PREFETCH_EXCLUSIVE` mnemonic name (Fixes #215)
- Updated instruction definitions for various AVX512 instructions
- Applied various documentation improvements (Fixes #347)

Co-authored-by: marjevan <marjevan@users.noreply.github.com>

Author: sdeadmin

VERSION

@@ -1 +1 @@
-v2025.03.02
+v2025.06.08

…tafiles/avx10-2/avx10-256rc-evex-dec.txt …tafiles/amd/amdxop/amd-xop-reg-table.txtdatafiles/avx10-2/avx10-256rc-evex-dec.txt renamed to datafiles/amd/amdxop/amd-xop-reg-table.txt datafiles/avx10-2/avx10-256rc-evex-dec.txt renamed to datafiles/amd/amdxop/amd-xop-reg-table.txt

@@ -1,6 +1,6 @@
 #BEGIN_LEGAL
 #
-#Copyright (c) 2024 Intel Corporation
+#Copyright (c) 2025 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -16,20 +16,19 @@
 #  
 #END_LEGAL
 
-# For reg/reg ops with rounding control, we have to avoid having the
-#  RC bits mess up the length. So we fix them here.
-FIX_ROUND_LEN256()::
-mode16 | VL256 VL_IGN=1
-mode32 | VL256 VL_IGN=1
-mode64 | VL256 VL_IGN=1
+# VGPRy_N, VGPRy_B, and VGPRy_R are used by AMD XOP.
 
-AVX256_ROUND()::
-BCRC=1 UBIT=0 LLRC=0b00 | ROUNDC=1 SAE=1
-BCRC=1 UBIT=0 LLRC=0b01 | ROUNDC=2 SAE=1
-BCRC=1 UBIT=0 LLRC=0b10 | ROUNDC=3 SAE=1
-BCRC=1 UBIT=0 LLRC=0b11 | ROUNDC=4 SAE=1
-#Default: otherwise | error
+xed_reg_enum_t VGPRy_R()::   
+EOSZ=1 | OUTREG=VGPR32_R() 
+EOSZ=2 | OUTREG=VGPR32_R()
+EOSZ=3 | OUTREG=VGPR64_R()
 
-SAE256()::
-BCRC=1 UBIT=0 | SAE=1
-#Default: otherwise | error
+xed_reg_enum_t VGPRy_B()::   
+EOSZ=1 | OUTREG=VGPR32_B() 
+EOSZ=2 | OUTREG=VGPR32_B()
+EOSZ=3 | OUTREG=VGPR64_B() 
+
+xed_reg_enum_t VGPRy_N()::   
+EOSZ=1 | OUTREG=VGPR32_N() 
+EOSZ=2 | OUTREG=VGPR32_N()
+EOSZ=3 | OUTREG=VGPR64_N() 

datafiles/amd/amdxop/files.cfg

@@ -1,6 +1,6 @@
 #BEGIN_LEGAL
 #
-#Copyright (c) 2020 Intel Corporation
+#Copyright (c) 2025 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -18,7 +18,8 @@
 
 state:xop-state-bits.txt
 
-
+dec-patterns : amd-xop-reg-table.txt
+enc-dec-patterns : amd-xop-reg-table.txt
 dec-patterns:amd-xop-dec.txt
 dec-instructions:amd-xop-isa.txt
 enc-instructions:amd-xop-isa.txt

datafiles/amd/xed-amd-invlpgb.txt

@@ -1,6 +1,6 @@
 #BEGIN_LEGAL
 #
-#Copyright (c) 2020 Intel Corporation
+#Copyright (c) 2025 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -25,13 +25,13 @@ EXTENSION : AMD_INVLPGB
 ATTRIBUTES: AMDONLY
 COMMENT   : Is this 64b mode only?
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] no_refining_prefix eamode32
-OPERANDS  : REG0=XED_REG_EAX:r:IMPL \
-            REG1=XED_REG_EDX:r:IMPL \
-            REG2=XED_REG_ECX:r:IMPL 
+OPERANDS  : REG0=XED_REG_EAX:r:SUPP \
+            REG1=XED_REG_EDX:r:SUPP \
+            REG2=XED_REG_ECX:r:SUPP 
 PATTERN   : 0x0F 0x01 MOD[0b11] MOD=3 REG[0b111] RM[0b110] no_refining_prefix eamode64
-OPERANDS  : REG0=XED_REG_RAX:r:IMPL \
-            REG1=XED_REG_EDX:r:IMPL \
-            REG2=XED_REG_ECX:r:IMPL 
+OPERANDS  : REG0=XED_REG_RAX:r:SUPP \
+            REG1=XED_REG_EDX:r:SUPP \
+            REG2=XED_REG_ECX:r:SUPP 
 }
 {
 ICLASS    : TLBSYNC

datafiles/amx-dmr/amx-dmr-isa.xed.txt

@@ -1,6 +1,6 @@
 #BEGIN_LEGAL
 #
-#Copyright (c) 2024 Intel Corporation
+#Copyright (c) 2025 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -228,7 +228,7 @@ ISA_SET:     AMX_TRANSPOSE
 EXCEPTIONS:  AMX-E11
 REAL_OPCODE: Y
 ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0x6E VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
+PATTERN:     VV1 0x6E VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
 OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
 IFORM:       T2RPNTLVWZ0_TMM2u16_MEMu16
 }
@@ -244,7 +244,7 @@ ISA_SET:     AMX_TRANSPOSE_MOVRS
 EXCEPTIONS:  AMX-E11
 REAL_OPCODE: Y
 ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0xF8 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
+PATTERN:     VV1 0xF8 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
 OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
 IFORM:       T2RPNTLVWZ0RS_TMM2u16_MEMu16
 }
@@ -260,7 +260,7 @@ ISA_SET:     AMX_TRANSPOSE_MOVRS
 EXCEPTIONS:  AMX-E11
 REAL_OPCODE: Y
 ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0xF9 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
+PATTERN:     VV1 0xF9 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
 OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
 IFORM:       T2RPNTLVWZ0RST1_TMM2u16_MEMu16
 }
@@ -276,7 +276,7 @@ ISA_SET:     AMX_TRANSPOSE
 EXCEPTIONS:  AMX-E11
 REAL_OPCODE: Y
 ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0x6F VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
+PATTERN:     VV1 0x6F VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
 OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
 IFORM:       T2RPNTLVWZ0T1_TMM2u16_MEMu16
 }
@@ -292,7 +292,7 @@ ISA_SET:     AMX_TRANSPOSE
 EXCEPTIONS:  AMX-E11
 REAL_OPCODE: Y
 ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0x6E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
+PATTERN:     VV1 0x6E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
 OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
 IFORM:       T2RPNTLVWZ1_TMM2u16_MEMu16
 }
@@ -308,7 +308,7 @@ ISA_SET:     AMX_TRANSPOSE_MOVRS
 EXCEPTIONS:  AMX-E11
 REAL_OPCODE: Y
 ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0xF8 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
+PATTERN:     VV1 0xF8 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
 OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
 IFORM:       T2RPNTLVWZ1RS_TMM2u16_MEMu16
 }
@@ -324,7 +324,7 @@ ISA_SET:     AMX_TRANSPOSE_MOVRS
 EXCEPTIONS:  AMX-E11
 REAL_OPCODE: Y
 ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0xF9 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
+PATTERN:     VV1 0xF9 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
 OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
 IFORM:       T2RPNTLVWZ1RST1_TMM2u16_MEMu16
 }
@@ -340,7 +340,7 @@ ISA_SET:     AMX_TRANSPOSE
 EXCEPTIONS:  AMX-E11
 REAL_OPCODE: Y
 ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0x6F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
+PATTERN:     VV1 0x6F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
 OPERANDS:    REG0=TMM_R():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
 IFORM:       T2RPNTLVWZ1T1_TMM2u16_MEMu16
 }
@@ -452,7 +452,7 @@ ISA_SET:     AMX_MOVRS
 EXCEPTIONS:  AMX-E3
 REAL_OPCODE: Y
 ATTRIBUTES:  NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0x4A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
+PATTERN:     VV1 0x4A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
 OPERANDS:    REG0=TMM_R():w:tv:u32 MEM0:r:ptr:u32
 IFORM:       TILELOADDRS_TMMu32_MEMu32
 }
@@ -468,7 +468,7 @@ ISA_SET:     AMX_MOVRS
 EXCEPTIONS:  AMX-E3
 REAL_OPCODE: Y
 ATTRIBUTES:  NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0x4A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
+PATTERN:     VV1 0x4A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
 OPERANDS:    REG0=TMM_R():w:tv:u32 MEM0:r:ptr:u32
 IFORM:       TILELOADDRST1_TMMu32_MEMu32
 }

datafiles/amx-dmr/cpuid.xed.txt

@@ -1,6 +1,6 @@
 #BEGIN_LEGAL
 #
-#Copyright (c) 2024 Intel Corporation
+#Copyright (c) 2025 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -19,7 +19,7 @@
 XED_ISA_SET_AMX_FP8             : amx_fp8.1e.1.eax.4
 XED_ISA_SET_AMX_TRANSPOSE       : amx_transpose.1e.1.eax.5
 XED_ISA_SET_AMX_TF32            : amx_tf32.1e.1.eax.6
-XED_ISA_SET_AMX_AVX512          : amx_avx512.1e.1.eax.7 avx10_enabled.7.1.edx[19] avx10_ver2.24.0.ebx[0:7]=2 avx10_512vl.24.0.ebx[18]
+XED_ISA_SET_AMX_AVX512          : amx_avx512.1e.1.eax.7
 XED_ISA_SET_AMX_MOVRS           : amx_movrs.1e.1.eax.8
 
 XED_ISA_SET_AMX_TRANSPOSE_MOVRS : amx_transpose.1e.1.eax.5 amx_movrs.1e.1.eax.8

datafiles/amx-spr/amx-spr-isa.xed.txt

@@ -1,6 +1,6 @@
 #BEGIN_LEGAL
 #
-#Copyright (c) 2024 Intel Corporation
+#Copyright (c) 2025 Intel Corporation
 #
 #  Licensed under the Apache License, Version 2.0 (the "License");
 #  you may not use this file except in compliance with the License.
@@ -147,7 +147,7 @@ ISA_SET:     AMX_TILE
 EXCEPTIONS:  AMX-E3
 REAL_OPCODE: Y
 ATTRIBUTES:  NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0x4B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
+PATTERN:     VV1 0x4B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
 OPERANDS:    REG0=TMM_R():w:tv:u32 MEM0:r:ptr:u32
 IFORM:       TILELOADD_TMMu32_MEMu32
 }
@@ -163,7 +163,7 @@ ISA_SET:     AMX_TILE
 EXCEPTIONS:  AMX-E3
 REAL_OPCODE: Y
 ATTRIBUTES:  NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0x4B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
+PATTERN:     VV1 0x4B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
 OPERANDS:    REG0=TMM_R():w:tv:u32 MEM0:r:ptr:u32
 IFORM:       TILELOADDT1_TMMu32_MEMu32
 }
@@ -195,7 +195,7 @@ ISA_SET:     AMX_TILE
 EXCEPTIONS:  AMX-E3
 REAL_OPCODE: Y
 ATTRIBUTES:  NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     VV1 0x4B VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() W0 VL128 mode64 NOVSR
+PATTERN:     VV1 0x4B VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB W0 VL128 mode64 NOVSR
 OPERANDS:    MEM0:w:ptr:u32 REG0=TMM_R():r:tv:u32
 IFORM:       TILESTORED_MEMu32_TMMu32
 }

datafiles/apx-f/README.md

@@ -7,7 +7,7 @@ Intel® XED decoder and encoder fully support Intel® APX.
 for a couple of legacy instructions.
 
 # Useful APIs
-Numerous examples and vivid explanations regarding Intel® APX features can be found in the xed-ex1 example tool.
+Numerous examples and vivid explanations regarding Intel® APX features can be found in the xed-dec example tool.
 
 Encode request for promoted No-Flags instruction should be built with the `NF` operand:
 

datafiles/apx-f/apx-f-amx-isa.xed.txt

@@ -67,7 +67,7 @@ ISA_SET:     APX_F_AMX_TRANSPOSE
 EXCEPTIONS:  AMX-E11-EVEX
 REAL_OPCODE: Y
 ATTRIBUTES:  DISP8_NO_SCALE MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     EVV 0x6E VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() BCRC=0 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN:     EVV 0x6E VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB BCRC=0 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
 OPERANDS:    REG0=TMM_R3():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
 IFORM:       T2RPNTLVWZ0_TMM2u16_MEMu16_APX
 }
@@ -83,7 +83,7 @@ ISA_SET:     APX_F_AMX_TRANSPOSE_MOVRS
 EXCEPTIONS:  AMX-E11-EVEX
 REAL_OPCODE: Y
 ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     EVV 0xF8 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() BCRC=0 W0 VL128 mode64 NOEVSR MASK=0
+PATTERN:     EVV 0xF8 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB BCRC=0 W0 VL128 mode64 NOEVSR MASK=0
 OPERANDS:    REG0=TMM_R3():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
 IFORM:       T2RPNTLVWZ0RS_TMM2u16_MEMu16_APX
 }
@@ -99,7 +99,7 @@ ISA_SET:     APX_F_AMX_TRANSPOSE_MOVRS
 EXCEPTIONS:  AMX-E11-EVEX
 REAL_OPCODE: Y
 ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     EVV 0xF9 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() BCRC=0 W0 VL128 mode64 NOEVSR MASK=0
+PATTERN:     EVV 0xF9 VNP MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB BCRC=0 W0 VL128 mode64 NOEVSR MASK=0
 OPERANDS:    REG0=TMM_R3():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
 IFORM:       T2RPNTLVWZ0RST1_TMM2u16_MEMu16_APX
 }
@@ -115,7 +115,7 @@ ISA_SET:     APX_F_AMX_TRANSPOSE
 EXCEPTIONS:  AMX-E11-EVEX
 REAL_OPCODE: Y
 ATTRIBUTES:  DISP8_NO_SCALE MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     EVV 0x6F VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() BCRC=0 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN:     EVV 0x6F VNP V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB BCRC=0 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
 OPERANDS:    REG0=TMM_R3():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
 IFORM:       T2RPNTLVWZ0T1_TMM2u16_MEMu16_APX
 }
@@ -131,7 +131,7 @@ ISA_SET:     APX_F_AMX_TRANSPOSE
 EXCEPTIONS:  AMX-E11-EVEX
 REAL_OPCODE: Y
 ATTRIBUTES:  DISP8_NO_SCALE MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     EVV 0x6E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() BCRC=0 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN:     EVV 0x6E V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB BCRC=0 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
 OPERANDS:    REG0=TMM_R3():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
 IFORM:       T2RPNTLVWZ1_TMM2u16_MEMu16_APX
 }
@@ -147,7 +147,7 @@ ISA_SET:     APX_F_AMX_TRANSPOSE_MOVRS
 EXCEPTIONS:  AMX-E11-EVEX
 REAL_OPCODE: Y
 ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     EVV 0xF8 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() BCRC=0 W0 VL128 mode64 NOEVSR MASK=0
+PATTERN:     EVV 0xF8 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB BCRC=0 W0 VL128 mode64 NOEVSR MASK=0
 OPERANDS:    REG0=TMM_R3():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
 IFORM:       T2RPNTLVWZ1RS_TMM2u16_MEMu16_APX
 }
@@ -163,7 +163,7 @@ ISA_SET:     APX_F_AMX_TRANSPOSE_MOVRS
 EXCEPTIONS:  AMX-E11-EVEX
 REAL_OPCODE: Y
 ATTRIBUTES:  MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     EVV 0xF9 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() BCRC=0 W0 VL128 mode64 NOEVSR MASK=0
+PATTERN:     EVV 0xF9 V66 MAP5 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB BCRC=0 W0 VL128 mode64 NOEVSR MASK=0
 OPERANDS:    REG0=TMM_R3():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
 IFORM:       T2RPNTLVWZ1RST1_TMM2u16_MEMu16_APX
 }
@@ -179,7 +179,7 @@ ISA_SET:     APX_F_AMX_TRANSPOSE
 EXCEPTIONS:  AMX-E11-EVEX
 REAL_OPCODE: Y
 ATTRIBUTES:  DISP8_NO_SCALE MULTIDEST2 NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     EVV 0x6F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() BCRC=0 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN:     EVV 0x6F V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB BCRC=0 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
 OPERANDS:    REG0=TMM_R3():w:tv:2u16:MULTIDEST2 MEM0:r:ptr:u16
 IFORM:       T2RPNTLVWZ1T1_TMM2u16_MEMu16_APX
 }
@@ -195,7 +195,7 @@ ISA_SET:     APX_F_AMX
 EXCEPTIONS:  AMX-E3-EVEX
 REAL_OPCODE: Y
 ATTRIBUTES:  DISP8_NO_SCALE NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     EVV 0x4B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() BCRC=0 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN:     EVV 0x4B VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB BCRC=0 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
 OPERANDS:    REG0=TMM_R3():w:tv:u32 MEM0:r:ptr:u32
 IFORM:       TILELOADD_TMMu32_MEMu32_APX
 }
@@ -211,7 +211,7 @@ ISA_SET:     APX_F_AMX_MOVRS
 EXCEPTIONS:  AMX-E3-EVEX
 REAL_OPCODE: Y
 ATTRIBUTES:  NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     EVV 0x4A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() BCRC=0 W0 VL128 mode64 NOEVSR MASK=0
+PATTERN:     EVV 0x4A VF2 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB BCRC=0 W0 VL128 mode64 NOEVSR MASK=0
 OPERANDS:    REG0=TMM_R3():w:tv:u32 MEM0:r:ptr:u32
 IFORM:       TILELOADDRS_TMMu32_MEMu32_APX
 }
@@ -227,7 +227,7 @@ ISA_SET:     APX_F_AMX_MOVRS
 EXCEPTIONS:  AMX-E3-EVEX
 REAL_OPCODE: Y
 ATTRIBUTES:  NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     EVV 0x4A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() BCRC=0 W0 VL128 mode64 NOEVSR MASK=0
+PATTERN:     EVV 0x4A V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB BCRC=0 W0 VL128 mode64 NOEVSR MASK=0
 OPERANDS:    REG0=TMM_R3():w:tv:u32 MEM0:r:ptr:u32
 IFORM:       TILELOADDRST1_TMMu32_MEMu32_APX
 }
@@ -243,7 +243,7 @@ ISA_SET:     APX_F_AMX
 EXCEPTIONS:  AMX-E3-EVEX
 REAL_OPCODE: Y
 ATTRIBUTES:  DISP8_NO_SCALE NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     EVV 0x4B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() BCRC=0 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN:     EVV 0x4B V66 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB BCRC=0 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
 OPERANDS:    REG0=TMM_R3():w:tv:u32 MEM0:r:ptr:u32
 IFORM:       TILELOADDT1_TMMu32_MEMu32_APX
 }
@@ -259,7 +259,7 @@ ISA_SET:     APX_F_AMX
 EXCEPTIONS:  AMX-E3-EVEX
 REAL_OPCODE: Y
 ATTRIBUTES:  DISP8_NO_SCALE NOTSX SPECIAL_AGEN_REQUIRED 
-PATTERN:     EVV 0x4B VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() BCRC=0 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
+PATTERN:     EVV 0x4B VF3 V0F38 MOD[mm] MOD!=3 REG[rrr] RM[0b100] MODRM() SIB BCRC=0 W0 VL128 mode64 NOEVSR ZEROING=0 MASK=0
 OPERANDS:    MEM0:w:ptr:u32 REG0=TMM_R3():r:tv:u32
 IFORM:       TILESTORED_MEMu32_TMMu32_APX
 }

datafiles/apx-f/cpuid.xed.txt

@@ -44,7 +44,7 @@ XED_ISA_SET_APX_F_KOPW        : apx_f.7.1.edx.21 avx512f.7.0.ebx.16
 XED_ISA_SET_APX_F_KOPD        : apx_f.7.1.edx.21 avx512bw.7.0.ebx.30
 XED_ISA_SET_APX_F_KOPQ        : apx_f.7.1.edx.21 avx512bw.7.0.ebx.30
 ### KOP AVX10 CPUID bits
-XED_ISA_SET_APX_F_KOPB, AVX10 : apx_f.7.1.edx.21 avx10_enabled.7.1.edx[19] avx10_ver1.24.0.ebx[0:7]=1 avx10_256vl.24.0.ebx[17]
-XED_ISA_SET_APX_F_KOPW, AVX10 : apx_f.7.1.edx.21 avx10_enabled.7.1.edx[19] avx10_ver1.24.0.ebx[0:7]=1 avx10_256vl.24.0.ebx[17]
-XED_ISA_SET_APX_F_KOPD, AVX10 : apx_f.7.1.edx.21 avx10_enabled.7.1.edx[19] avx10_ver1.24.0.ebx[0:7]=1 avx10_256vl.24.0.ebx[17]
-XED_ISA_SET_APX_F_KOPQ, AVX10 : apx_f.7.1.edx.21 avx10_enabled.7.1.edx[19] avx10_ver1.24.0.ebx[0:7]=1 avx10_256vl.24.0.ebx[17]
+XED_ISA_SET_APX_F_KOPB, AVX10 : apx_f.7.1.edx.21 avx10_enabled.7.1.edx[19] avx10_ver1.24.0.ebx[0:7]=1
+XED_ISA_SET_APX_F_KOPW, AVX10 : apx_f.7.1.edx.21 avx10_enabled.7.1.edx[19] avx10_ver1.24.0.ebx[0:7]=1
+XED_ISA_SET_APX_F_KOPD, AVX10 : apx_f.7.1.edx.21 avx10_enabled.7.1.edx[19] avx10_ver1.24.0.ebx[0:7]=1
+XED_ISA_SET_APX_F_KOPQ, AVX10 : apx_f.7.1.edx.21 avx10_enabled.7.1.edx[19] avx10_ver1.24.0.ebx[0:7]=1